Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Stacy W Hall

Miguel A Delgado

Andrew J Black

Eric A Sparks

Pierre Leroux

Anthony Sayka

Allen Page

Edward R Vokoun, Iii

Judy U Galloway

Bryan D Schmidt

Daniel D Siems

Henry B Taylor, Iii

A system and method are provided that maintains a high pH at the wafer surface through the entire polish process and then lowers the pH only when necessary in a controlled fashion after CMP and during the post-polish clean. A fluid having a high pH chemistry and, optionally, surfactants is used instead of deionized water to keep the wafer and polisher components wet and to clean the slurry residue from the polishing pad.

Constant pH polish and scrub

An integrated circuit structure includes a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Method of making an integrated circuit structure with planarized layer

An integrated circuit structure including a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Integrated circuit structure with self-planarized layers

Method and apparatus for detecting the presence of selected types of defects, such as chemical stains from a liquid photoresist material or a liquid dielectric material, on a non-visible chosen surface of a semiconductor water that has undergone at least one processing step. In one embodiment, a support substrate for, the wafer is provided that has a highly reflecting surface adjacent to the chosen surface. The reflecting surface and the chosen surface are moved apart, and the chosen surface is illuminated with light to form an optical image of the chosen surface. The optical image of the chosen surface is reflected in the reflecting surface, and the reflected optical image is examined for the presence of selected types of defects. In another embodiment, a portion of this reflecting surface is initially contiguous to the chosen surface. A selected defect, if any, on the chosen surface changes a surface characteristic of the reflecting surface so that the presence of this defect on the chosen surface is visually perceptible on the reflecting surface.

Semiconductor wafer defect monitoring

An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area. The second recessed area extends from the bottom of the first recessed area completely through the remaining oxide layer to the underlying metallic layer. In so doing, when amorphous silicon is deposited into the vias, cusping of the amorphous silicon within the vias is substantially reduced. As a result, the step of depositing a spacer oxide to fill in notches created by cusping of the amorphous silicon layer is eliminated. Consequently, when the amorphous silicon is removed or etched from selected strap vias, because no spacer oxide has been deposited, no deleterious residue or 'dog ears' of amorphous silicon remain within the strap vias.

Wet/dry anti-fuse via etch

A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.

Method for manufacturing anti-fuse structures

After a metal deposition is patterned using a plasma etch, the metal pattern is sprayed with steam and water. During the spraying the wafer is rotated to ensure proper distribution and removal of the spray. The spray removes chlorine residue from the etch that might otherwise corrode the metal pattern. After the spray, the spin rate is increased to dry the wafer. The net result is a faster and more effective method for chlorine removal from a plasma-etched metal pattern.

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San Antonio, TX, United States of America

Stacy W Hall