Dalsa Corporation

Imra America, Inc.

Stacy R Kamasz

Mark P Bendett

Michael George Farrier

Michael G Farrier

Fred S Ma

Simon Gareth Ingram

Savvas G Chamberlain

Martin Joseph Kiik

Carl D Leonard

Suhail Agwani

A sensor includes an array of pixels organized in rows and columns and a plurality of metal busses overlaying the array of pixels. A first column of pixels includes a proximal set of first pixels and a distal set of first pixels separated by a first jog region. A second column of pixels includes a proximal set of second pixels and a distal set of second pixels separated by a second jog region. The first jog region is displaced in a column direction and in a lateral direction transverse to the column direction from the second jog region. A first metal bus is insulatively disposed over both the first and second jog regions.

Reticulated gate CCD pixel with diagonal strapping

A circuit includes a circuit chip and a plurality of clock drivers external to the circuit chip. The circuit chip includes a plurality of isolated clocking subunits and a corresponding plurality of terminals. Each clocking subunit is electrically isolated from any other clocking subunit. Each clocking subunit is coupled to a respective terminal. For each of the plurality of terminals, an output from one and only one clock driver of the plurality of clock drivers is coupled to the corresponding terminal of the plurality of terminals, and inputs of all clock drivers are coupled together.

Arrangements of clock line drivers

A CCD structure includes a substrate in which a plurality of buried channels have been formed and a heat conductor disposed transversely to the buried channels and defining a longitudinal direction. A first channel defines a channel direction. The heat conductor includes a first segment and a second segment separated by a gap from the first segment. The heat conductor further includes a tab connected to the first segment. In the structure the tab is characterized by an extent along a direction parallel to the longitudinal direction that is equal to an extent of the gap along the longitudinal direction, an extent along a direction perpendicular to the longitudinal direction that is equal to a width of the heat conductor, and a shape that is a parallelogram, preferrably a rectangle. In the structure the gap is characterized by a gap predetermined shape, size and orientation, and the tab is characterized by a tab predetermined shape, size and orientation. The tab predetermined shape, size and orientation is equal to the gap predetermined shape, size and orientation, respectively.

CCD sensor with diagonal heat conducting straps

In a charge coupled device having a plurality of output structures, the plurality of output structures including first and second output structures, a channel structure is defined in a channel region beneath a gate electrode and coupled to each of the plurality of output structures. The channel structure includes a plurality of area structures, each area structure being characterized by a uniform potential which is different from the potential characterizing each of the other area structures. The plurality of area structures are arranged within the channel region to define a first increasing stepped potential gradient from any point within the channel region to the first output structure and define a second increasing stepped potential gradient from any point within the channel region to the second output structure. A length of each area structure traversing the area structure in a first gradient direction is less than or equal to a first critical length, the first critical length being defined by a first desired transfer time for transferring charge to the first output structure. A length of each area structure traversing the area structure in a second gradient direction is less than or equal to a second critical length, the second critical length being defined by a second desired transfer time for transferring charge to the second output structure.

Efficient charge transfer structure in large pitch charge coupled device

Accordingly, the present invention is directed to providing methods and apparatus for detecting light energy in real-time while minimizing the effects of background charge accrual on the charge-coupled device. Exemplary embodiments provide relatively fast electronic shuttering and exposure control to minimize accrual of unwanted background illumination. Further, exemplary embodiments can be operated at relatively high speeds without increasing the complexity of electronics used to drive the charge-coupled device or process information produced by the charge-coupled device.

Charge coupled device pulse discriminator

A CCD shift register includes a second gate electrode disposed adjacent to and longitudinally spaced from a first gate electrode, and a buried layer having a first dopant impurity concentration. The first gate electrode is disposed over the buried layer to define a first buried layer area. The second gate electrode is disposed over the buried layer to define a second buried layer area greater than the first buried layer area. In the buried layer, a trench region is formed to have a second dopant impurity concentration greater than the first dopant impurity concentration. The first gate electrode is disposed over the trench region to define a first trench area. The second gate electrode being disposed over the trench region to define a second trench area less than the first trench area. The first and second trench areas are dimensioned so that a first charge storage capacity is equal to or greater than a second charge storage capacity. A tapped CCD shift register includes a first CCD shift register segment and a second shift register segment, both the first and second CCD shift register segments being characterized by a pitch length in the longitudinal direction. The first CCD shift register segment includes a sense node, and the second CCD shift register segment includes a beginning shift register charge storage element, both the sense node and the beginning shift register charge storage element being disposed within one pitch length in the longitudinal direction.

Method of making CCD readout register having multiple outputs

A CCD shift register includes a first gate electrode, a second gate electrode disposed adjacent to and longitudinally spaced from the first gate electrode, and a buried layer having a first dopant impurity concentration. The first gate electrode is disposed over the buried layer so as to define a first buried layer area. The second gate electrode is disposed over the buried layer so as to define a second buried layer area greater than the first buried layer area. In the buried layer, a trench region is formed so as to have a second dopant impurity concentration greater than the first dopant impurity concentration. The first gate electrode is disposed over the trench region so as to define a first trench area. The second gate electrode being disposed over the trench region so as to define a second trench area less than the first trench area. In the CCD shift register, the first buried layer area defines an area for a first charge storage element characterized by a first charge storage capacity, the first charge storage capacity being a function of the first trench area. The second buried layer area defines an area for a second charge storage element characterized by a second charge storage capacity, the second charge storage capacity being a function of the second trench area. The first and second trench areas are dimensioned so that the first charge storage capacity is equal to or greater than the second charge storage capacity. A tapped CCD shift register includes a first CCD shift register segment and a second shift register segment, both the first and second CCD shift register segments being characterized by a pitch length in the longitudinal direction. The first CCD shift register segment includes a sense node, and the second CCD shift register segment includes a beginning shift register charge storage element, both the sense node and the beginning shift register charge storage element being disposed within one pitch length in the longitudinal direction.

Variable width CCD register with uniform pitch and charge storage

The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.

Method and apparatus for real-time background illumination subtraction

The present invention is directed to providing a charge-coupled device which can provide accurate signal detection while providing high speed electronic exposure control or shuttering. Exemplary embodiments can maintain charge transfer efficiency at a relatively high level even if a pixel array of the charge-coupled device is clocked rapidly (i.e., exposure control or shuttering speed is increased) for a given pixel pitch.

Growing community of inventors

Waterloo, Canada

Stacy R Kamasz