International Business Machines Corporation

Globalfoundries Inc.

Stacy J Garvin

Hayden C Cranford, Jr

Vernon Roberts Norman

Todd Morgan Rasmus

Martin L Schmatz

Hayden Cranford

Joseph M Stevens

Paul Alan Owczarski

John Paul Rankin

John Francis Bulzacchelli

Francois Ibrahim Atallah

Geoffrey B Stephens

Peter Robert Seidel

David W Nuechterlein

Samuel Taylor Ray

John M Mullen

Wendy K Hodgin

Wayne A Utter

Circuits for an analog-to-digital converter and methods of operating an analog-to-digital converter. A resistor digital-to-analog converter (RDAC) has a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAC is configured to generate a second voltage including a first voltage shift from the first voltage and to supply the second voltage from the output port of the RDAC to the buffer.

Analog-to-digital converters with resistor digital-to-analog converters for reference voltage tuning

Circuits for a successive approximation register analog-to-digital converter and related methods. A global reference circuit includes a first super source follower (SSF) circuit having an input coupled to an output of a first current mirror and to a first adjustment circuit, and an operational amplifier having an input coupled to an output of the first SSF circuit and an output coupled to an input of the first current mirror. Local slices each include a second current mirror having an input coupled to the output of the operational amplifier, a second super source follower (SSF) circuit having an input coupled to an output of the second current mirror and to a second adjustment circuit. The first and second adjustment circuits may be configured to adjust a voltage at the input of the first SSF circuit and respective voltages at the input of the second SSF circuit of each local slice.

Temperature compensation for reference voltages in an analog-to-digital converter

A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.

Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)

A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

Transistor switch with integral body connection to prevent latchup

A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

Method and system for high frequency clock signal gating

The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

Analog unidirectional serial link architecture

Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

Circuit and method for reducing jitter in a PLL of high speed serial links

A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.

A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

Self-adaptive voltage regulator for a phase-locked loop

The present invention describes aspects of adjusting a frequency range of a delay cell of a VCO. The aspects include providing a CMOS latch of predetermined gain, and altering transconductance in the CMOS latch to alter a frequency range of the CMOS latch without altering the predetermined gain. The alteration of transconductance includes coupling at least one pair of series connected transistors in parallel with each switching device of the CMOS latch.

Method and system for adjusting a frequency range of a delay cell of a VCO

A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains. A second bias voltage is coupled to the PMOS devices in the first and second CMOS cascode chains. An output is provided from the second CMOS cascode chain to a third CMOS cascode chain for purposes of providing sufficient pullup capability to drive an output circuit comprising a fourth CMOS cascode chain between the high and reference potentials without exceeding the breakdown mechanisms for any MOS device in the CMOS cascode chains.

Low voltage CMOS circuit for on/off chip drive at high voltage

A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.

Fast content addressable memory with reduced power consumption

A level selectable FET voltage generation system is described. The system includes a single charge pump controlled by multiple feedback paths and a powerdown circuit. Each feedback path contains a capacitor divider network, a sense amplifier with a compensating voltage reference and a timer which periodically resets the capacitor divider network to insure sensing accuracy. The powerdown circuit and a selected feedback path provides a desired voltage level at the output of the charge pump.

On chip multiple voltage generation using a charge pump and plural

A voltage generating system provides a plurality of different voltages for powering a dynamic nonvolatile random access memory (NVRAM) chip. The voltage generating system includes a pair of charge pumps. Each charge pump is coupled to a controller that senses the voltage level at the output of the charge pump and generates an enabling signal when said voltage is at a predetermined value. The signal activates a power down circuit which adjusts the charge pump output to a desired voltage level. A programmable oscillator provides the clocking signals for the controller. The charge pumps and programmable oscillators are periodically deactivated. As a result, the overall power consumption of the chip is reduced.

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Durham, NC, United States of America

Stacy J Garvin