Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Stacy Ho

Michael Anthony Ashburn, Jr

Chan-Hsiang Weng

Tien-Yu Lo

Ayman Shabra

Wei-Hsin Tseng

Jeffrey Carl Gealow

Patrick Cooney

Gerhard Mitteregger

Nathan Egan

Tsung-Kai Kao

José Barreiro Da Silva

Chih-hong Lou

Kuan-hung Chen

Boyi Zheng

A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering comprises: a first DAC; an auxiliary code generator configured to produce an auxiliary code; an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code; and summing circuitry to dither LSBs of the first DAC with the auxiliary code. The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

LSB dithering for segmented DACs

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

Methods and circuits for suppressing quantization noise in digital-to-analog converters

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Anti-aliasing filter

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

Analog-to-digital converter with bandpass noise transfer function

An automatic gain control circuit includes an input gain stage for receiving and amplifying an analog input signal; an analog-to-digital converter for receiving the amplified analog input signal and providing a digital output signal; and an overload management module. The overload management module is arranged to receive the digital output signal; determine therefrom whether the received, amplified analog input signal exceeds an operating range of the analog-to-digital converter; and provide a first control signal to the input gain stage to adjust a gain of the input gain stage in response thereto.

Analog-to-digital converter circuit, integrated circuit, electronic device and method therefor

A segmented digital-to-analog converter (DAC) is disclosed. In the present invention, the segmented DAC of the present invention comprises a signal component processing stage and a plurality of noise component processing stages cascaded with the signal component processing stage. A noise component of an input word for the DAC is split into a plurality of portions to be processed. By doing so, effect due to gain mismatch(es) in an analog portion of the DAC can be effectively reduced without significantly increasing DAC cells used in the DAC.

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Reading, MA, United States of America

Stacy Ho