Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Richwave Technology Corp.

Ssu-Pin Ma

Yen-Shih Ho

Heng-Ming Hsu

Kong-Beng Thei

Ta-Hsun Yeh

Kuo-Reay Peng

Chun-Hon Chen

Chi-Wu Chou

Shyh-Chyi Wong

Wen-Wei Yang

Min Hung Shen

Shuw Guann Lin

Chen-Chung Kuo

Chao-Cheng Chen

Chaochieh Tsai

Shao-Hua Chen

Liang-Kun Huang

Jau-Yuann Chung

A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while resuming a normal charging/discharging thereafter, and vice versa. The present invention makes use of the turbo-charging/discharging for a linear compensation, such that the produced oscillating signal has the features of concurrently eliminating phase noises and jitters as well as maintaining the modulation linearity.

Turbo-charged relaxation oscillator method and apparatus

Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

Planar spiral inductor structure with patterned microelectronic structure integral thereto

A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (X/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (SiN) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer

This MIM structure provides metal capacitors with high figure of merit Q (X /R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si N ) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer

A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process

In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Dual damascene interconnect structures that include radio frequency capacitors and inductors

A new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second layer of metal form an inductor of increased height, reducing the resistivity of the inductor, increasing the Q value of the inductor. The new method of creating an inductor can be combined with creating contact points that connect to contact points in the active region of the surface of a semiconductor substrate.

High Q inductor with Cu damascene via/trench etching simultaneous module

A structure is disclosed for a multi-finger transistor with improved high frequency performance. An array of isolated active regions is formed in a semiconductor substrate. A source region and a drain region are formed in each of the active regions and are disposed on either side of a central channel region. A gate oxide layer is formed over each channel region. Conductive gate fingers that extend over the gate oxide layers and also beyond the active areas are formed so that each gate finger constitutes a continuous conductive line providing and connecting the gates of the plurality of active regions. A dielectric layer is formed over the active regions and over the surrounding isolation regions. A conductive via is formed through the dielectric layer to each source region and to each drain region. For each gate finger or conductive via is opened between the active region and at both ends of the finger contact region is formed over each conductive via. Conductive lines are formed connecting together all the contact regions disposed over source regions, connecting together all the contact regions disposed over drain regions and connecting together all the contact regions disposed over gate fingers.

Chain gate MOS structure

A wireless LAN RF module uses parasitic element compensation devices in an antenna select circuit to improve port isolation. In addition, various combinations of RC filter networks and spurious radiation attenuators are incorporated into the Quad Demod/Mod and Synthesizer ;/circuits to provide suppression of EMI susceptibility and radiation throughout the RF module.

Wireless transmitter/receiver utilizing DSSS technology

Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow

A wireless LAN RF module uses a low power transistor switchable voltage divider circuit to control the bias input of a GaAs MESFET output power amplifier. This bias control circuit provides stable, high speed on-off switching of the power amplifier stage by applying low power bias voltages to the MESFET gate input, rather than by interrupting the high power MESFET drain to Vdd circuit.

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Taipei, Taiwan

Ssu-Pin Ma