Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

Analog Devices Global Unlimited Company

Srivatsan Parthasarathy

Javier Alejandro Salcedo

Shuyun Zhang

James Zhao

Rodrigo Carrillo-Ramirez

Yuanzhong Zhou

Padraig Fitzgerald

Michael C Coln

Linfeng He

Miguel Chanca

Sirui Luo

Lejun Hu

Jean-Jacques Hajjar

Enrique C Bosch

Franklin Marshall Murden, Ii

Ralph David Moore, Jr

Sandro Herrera

Nathan R Carter

Stuart Patterson

Daniel Boyko

Donal Bourke

Peter Delos

Thomas Paul Kearney

Piotr Olejarz

Ara Arakelian

John P Guido

Charly El-Khoury

Naveen Dhull

Francisco Santos

Tom Pilling

Low capacitance silicon controlled rectifier (SCR) topologies for overvoltage protection are disclosed herein. In certain embodiments, an overvoltage protection circuit is connected between an RF signal pad and a ground signal pad. The overvoltage protection circuit includes a fin field-effect transistor (FinFET) SCR including a PNP bipolar transistor and an NPN bipolar transistor that are cross-coupled, a FinFET trigger circuit connected between an emitter of the PNP bipolar transistor and a base of the NPN bipolar transistor, and a linearity enhancement impedance connected between a reference voltage terminal and the emitter of the PNP bipolar transistor. In certain implementations, a FinFET diode is further included in series with the FinFET SCR with a cathode of the FinFET diode connected to the emitter of the PNP bipolar transistor.

Low capacitance silicon controlled rectifier topology for overvoltage protection

Monolithic microwave integrated circuits (MMICs) tolerant to electrical overstress are provided. In certain embodiments, a MMIC includes a signal pad that receives a radio frequency (RF) signal, and an RF circuit coupled to the RF signal pad. The RF circuit includes a transistor layout, an input field-effect transistor (FET) implemented using a first portion of a plurality of gate fingers of the transistor layout, and an embedded protection device electrically connected between a gate and a source of the input FET and implemented using a second portion of the plurality of gate fingers. The MMIC is tolerant to electrical overstress events, such as field-induced charged-device model (FICDM) events.

Monolithic microwave integrated circuits tolerant to electrical overstress

Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

Electrostatic discharge protection for high speed transceiver interface

Electrical overstress protection for high speed interfaces are disclosed. In certain embodiments, a semiconductor die with bidirectional protection against electrical overstress is provided. The semiconductor die includes a first pad, a second pad, a forward protection silicon controlled rectifier (SCR) electrically connected between the first pad and the second pad and configured to activate in response to electrical overstress that increases a voltage of the first pad relative to a voltage of the second pad, and a reverse protection SCR electrically connected in parallel with the forward protection SCR between the first pad and the second pad and configured to activate in response to electrical overstress that decreases the voltage of the first pad relative to the voltage of the second pad.

Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces

Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.

Electrostatic discharge and overdrive protection circuitry

Electrical overstress protection of microelectromechanical systems (MEMS) are disclosed herein. In certain embodiments, a MEMS radio frequency system includes a MEMS device electrically connected along a radio frequency signal path that handles a radio frequency signal, and an electrical overstress protection circuit in shunt with the radio frequency signal path and operable to protect the MEMS device from an electrical overstress event, such as an electrostatic discharge (ESD) event received on the radio frequency signal path. The electrical overstress protection circuit includes a metal conductor configured to resonate about at a fundamental frequency of the radio frequency signal.

Electrical overstress protection of microelectromechanical systems

High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

High voltage clamps with transient activation and activation release control

Microwave amplifiers tolerant to electrical overstress are provided. In certain embodiments, a monolithic microwave integrated circuit (MMIC) includes a signal pad that receives a radio frequency (RF) signal, a ground pad, a balun including a primary section that receives the RF signal and a secondary section that outputs a differential RF signal, an amplifier that amplifies the differential RF signal, and a plurality of decoupling elements, some of them electrically connected between the primary section and the ground pad, others electrically connected in the secondary section to a plurality of the amplifier's nodes, and operable to protect the amplifier from electrical overstress. Such electrical overstress events can include electrostatic discharge (ESD) events, such as field-induced charged-device model (FICDM) events, as well as other types of overstress conditions.

Microwave amplifiers tolerant to electrical overstress

High voltage tolerant electrical overstress protection with low leakage current and low capacitance is provided. In one embodiment, a semiconductor die includes a signal pad, an internal circuit electrically connected to the signal pad, a power clamp electrically connected to an isolated node, and one or more isolation blocking voltage devices electrically connected between the signal pad and the isolated node. The one or more isolation blocking voltage devices are operable to isolate the signal pad from a capacitance of the power clamp. In another embodiment, a semiconductor die includes a signal pad, a ground pad, a high voltage/high speed internal circuit electrically connected to the signal pad, and a first thyristor and a second thyristor between the signal pad and the ground pad.

In certain configurations, an input/output (IO) interface of a semiconductor chip includes a pin, an interface switch connected to the pin, and an overstress detection and active control circuit that controls a resistance of the interface switch with active feedback. The overstress detection and active control circuit increases a resistance of the interface switch in response to detection of a transient overstress event between a first node and a second node. Accordingly, the overstress detection and active control circuit provides separate detection and logic control to selectively modify the resistance of the interface switch such that the interface switch operates with low resistance during normal operating conditions and with high resistance during overstress conditions.

Active interface resistance modulation switch

High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.

A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.

Apparatus for automotive and communication systems transceiver interfaces

Electrical overstress protection via silicon controlled rectifier (SCR) trigger amplification control is provided. In certain configurations, an overstress protection circuit includes a control circuit for detecting presence of an overstress event between a first pad and a second pad of an interface, and a discharge circuit electrically connected between the first pad and the second pad and selectively activated by the control circuit. The interface corresponds to an electronic interface of an integrated circuit (IC), a System on a Chip (SoC), or System in-a-Package (SiP). The discharge circuit includes a first smaller SCR and a second larger SCR. In response to detecting an overstress event, the control circuit activates the smaller SCR, which in turn activates the larger SCR to provide clamping between the first pad and the second pad.

Silicon controlled rectifier dynamic triggering and shutdown via control signal amplification

Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.

Fault tolerant low leakage switch

Micro-electromechanical switch (MEMS) devices can be fabricated using integrated circuit fabrication techniques and materials. Such switch devices can provide cycle life and insertion loss performance suiting for use in a broad range of applications including, for example, automated test equipment (ATE), switching for measurement instrumentation (such as a spectrum analyzer, network analyzer, or communication test system), and uses in communication systems, such as for signal processing. MEMS devices can be vulnerable to electrical over-stress, such as associated with electrostatic discharge (ESD) transient events. A solid-state clamp circuit can be incorporated in a MEMS device package to protect one or more MEMS devices from damaging overvoltage conditions. The clamp circuit can include single or multiple blocking junction structures having complementary current-voltage relationships, such as to help linearize a capacitance-to-voltage relationship presented by the clamp circuit.

Growing community of inventors

Acton, MA, United States of America

Srivatsan Parthasarathy