Synopsys, Inc.

Srivathsan Krishna Mohan

Qing Zhang

Paul Frain

Youming Xu

A method of identifying memory nodes includes reading a netlist of the design. For a sequential cell of the design, constraint arcs between constraint and related pins can be extracted. For each constraint arc, an original vector set including initialization waveforms can be generated. A plurality of simulations can be run using a plurality of vector sets to generate a plurality of node sets. Each simulation generates a corresponding node set that toggles based on waveforms provided by a corresponding vector set. Each vector set is derived from the original vector set. A final set of memory nodes for the sequential circuit cell can be calculated by subtracting one node set from another node set. In one embodiment, the method can further include pruning non-gate connected nodes from the final node set.

Constraint memory node identification in sequential logic

A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the final vectors are expressed only by primary inputs to the sequential circuit. Using only primary inputs in the final vectors accurately replicates the sequential circuit under test, thereby ensuring accurate timing, power, and noise arcs are measured.

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Mountain View, CA, United States of America

Srivathsan Krishna Mohan