Texas Instruments Corporation

Srivaths Ravi

Rubin Ajit Parekhji

Rajesh Kumar Tiwari

Amit Kumar Dutta

Sanjay Kumar

Swathi Gangasani

Prakash Narayanan

Alan David Hales

Wilson Pradeep

Srinivasulu Alampally

Raashid Moin Shaikh

Milan Shetty

Malav Shrikant Shah

Khushboo Agarwal

Srujan Kumar Nakidi

Sanjay Krishna Hulical Vijayaraghavachar

Divya Divakaran

Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

Testing of integrated circuits during at-speed mode of operation

This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.

Scan compression architecture with bypassable scan chains for low test mode power

A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Circuits and methods for dynamic allocation of scan test resources

An electronic circuit () for use with an accessing circuit () that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit () includes a memory circuit () accessible at addresses, an address buffer (), a data buffer () coupled to the memory circuit (), and a control circuit () operable in the dummy cycles to read data from the memory circuit () to the data buffer () from a next address location in the memory circuit () and to store that next address in the address buffer (). The electronic circuit further includes a multiplexer (), a comparing circuit () responsive to the given address and a stored address in the address buffer (), to operate the multiplexer () to pass data from the data buffer () or to pass data from the memory circuit () instead; and a mixer circuit () operable to put the partial write data portion into the data taken from the selected one of the data buffer () or memory circuit (). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs including a high compression codec and a low compression codec. The test engineer generates a first set of test patterns using the high compression codec. If this high compression results in unacceptable fault coverage loss, the top-up patterns for additional coverage are generated using the low compression codec. The invention may use multiple codecs serially one after the other. The codecs can be of different types or parameters (such as compression ratio, debug tolerance and combinational codec versus sequential codec).

Hybrid test compression architecture using multiple codecs for low pin count and high compression devices

This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.

On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability

A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.

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Bengaluru, India

Srivaths Ravi