Silicon Laboratories Inc.

Skyworks Solutions, Inc.

Srisai Rao Seethamraju

William Anker

Aslamali A Rafi

Rajesh Thirugnanam

Russell Croman

James David Barnette

Ronald B Hulfachor

Timothy A Monk

Joseph D Cali

Raghunandan Kolar Ranganathan

Kannanthodath V Jayakumar

Richard J Juhn

Michael Henderson Perrott

Jerrell P Hein

Xue-Mei Gong

Qicheng Yu

Harihara Subramanian Ranganathan

Kenneth Kin Wai Wong

Shailesh Chitnis

Rahul Shukla

Nathan J Shashoua

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

Synchronizing update of time of day counters using time stamp exchange over a control plane

A method for estimating jitter of a clock-signal-under-test includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method includes generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the phase-adjusted clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter estimate using an estimated standard deviation of a distribution of edges of the clock signal based on the N digital time codes for each of the P phase adjustments.

Jitter self-test using timestamps

A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

Correction for period error in a reference clock signal

A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

Method for generation of independent clock signals from the same oscillator

A method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.

A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Spur and quantization noise cancellation for PLLS with non-linear phase detection

A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2&#xd7; clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.

Noise canceling technique for a sine to square wave converter

A temperature compensated crystal oscillator (TCXO) includes a crystal oscillator and a temperature sensor to provide a sensed temperature. A delay circuit has a selectable delay to delay the frequency compensation based on the sensed temperature. The delay compensates for a difference between when the temperature sensor reflects a change in temperature and when a frequency of a signal supplied by the crystal oscillator is affected by the change in temperature. The delay may be static or dynamic with respect to the current temperature sensed by the temperature sensor.

Compensating for thermal lag in temperature compensated crystal oscillators

Hysteresis causes the temperature dependent frequency characteristic of the crystal of a crystal oscillator to be different when the temperature is rising from a previous colder state and when the temperature is falling from a hotter state. A rising temperature-to-frequency mapping polynomial and a falling temperature-to-frequency mapping polynomial are generated and their evaluations are weighted based on a current temperature and past temperature(s). The weighted evaluations are combined and used in temperature-based frequency compensation of the crystal oscillator.

Compensating for temperature-dependent hysteresis in a temperature compensated crystal oscillator

An amplifier topology achieves enhances DC gain to improve linearity while maintaining a good signal to noise ratio. The amplifier includes an amplifier output stage that supplies an amplifier output signal. The amplifier also includes a sense amplifier that augments the output stage. The sense amplifier is coupled to the amplifier input to control current through the output stage in order to achieve reduced voltage variation at the amplifier input as a function of the amplifier output signal voltage as compared to a basic common source amplifier and thereby enhances DC gain of the amplifier.

Amplifier topology achieving high DC gain and wide output voltage range

An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Glitchless clock switching that handles stopped clocks

A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.

Multiple signal format output driver with configurable internal load

A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Digital hold in a phase-locked loop

A crystal offset value is stored in non-volatile memory in an oscillator device. The crystal offset value corresponds to a ratio between a rated frequency of an output of a crystal oscillator and a measured frequency of the output of the crystal oscillator. A rated divide value that corresponds to a selected frequency for an output of the oscillator device assumes the crystal oscillator operates at its rated or ideal frequency. Thus, the rated divide value corresponds to the rated frequency. The rated divide value is adjusted by the crystal offset value to generate an adjusted divide value and the adjusted divide value is used to generate an output signal of the oscillator device with the selected frequency.

Growing community of inventors

Nashua, NH, United States of America

Srisai Rao Seethamraju