Cirrus Logic Inc.

Centillium Communications, Inc.

Sriraman Chari

Anthony J O'Toole

Geary L Leger

Anthony J P O'Toole

A bi-level framing structure for DSL phone systems uses 4 KHz physical frames and mux data frames. The mux data frames each start with a sync byte and contain user payload bytes. A group of mux data frames are appended with forward-error-correction FEC bytes to make a codeword. The codeword is then partitioned into physical 4-KHz frames. The physical frames are transformed by an inverse fast-Fourier transform (IFFT) outputting symbols at 4 KHz for transmission. For high line rates, each codeword has S mux data frames and S physical frames. There are also at least S FEC bytes if error correction is enabled. However, for lower line rates, there are S physical frames but only S/M mux data frames in each codeword. The efficiency factor M is 1 for high line rates, but 4 for lower line rates. Reducing the number of mux data frames reduces the number of sync bytes in a codeword, decreasing overhead. The FEC bytes are spread among more physical frames, reducing error-correction overhead. The symbol rate and the rate of physical frames remains at 4 KHz, even at the lower line rate. The smaller number of bytes per symbol at the lower line rates is compensated for by reducing the number of mux data frames per 4 KHz frame, allowing larger, more efficient mux data frames and error correction to be used. Thus bandwidth efficiency is increased for lower line rates.

Bi-level framing structure for improved efficiency DSL over noisy lines

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors. No matter in which order the individual channels of the multi-channel system use and return the data buffers, the available descriptors are maintained in contiguous locations in the descriptor queue, increasing the efficiency of the system since searching through the descriptor queue for available descriptors is not required.

System for managing direct memory access transfer in a multi-channel

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which a sequence of data frames are received at a controller that controls a DMA transfer. The data frames are placed in data buffers in a memory by the controller. Multiple data frames are stored by the controller in at least one of the data buffers. The storing of multiple data frames in a single buffer provides efficient utilization of memory space as large size buffers are used to hold more than a single data frame, and also reduces the management overhead involved in placing the data frames in the data buffers.

Method and apparatus for placing multiple frames of data in a buffer in

This invention provides efficient and flexible data transfer management for a First-In First-Out (FIFO) buffer connects to a system bus and implements multiple data thresholds (e.g., two). Data transfer by the FIFO is controlled by either casually or more aggressively acquiring the system bus based on the amount of data inside the FIFO and on the state of the system bus. By balancing the bus activity level against the FIFO data level, bus access is facilitated at times when the bus has lower activity. This makes the FIFO less obtrusive when moving data across the bus. As a result, the bus is used more efficiently. The system bus is casually acquired when the FIFO data level reaches a soft threshold and the system bus is idle. Casual control of the system bus is relinquished when request from another device sharing the bus is received and a predetermined amount of data has been transferred. On the other hand, the system bus is more aggressively acquired when the FIFO data level reaches a hard threshold. Aggressive control of the system bus is relinquished only when data transfer is complete or when there is an emergency condition such as bus error. The thresholds can be dynamically adjusted based on the bus activity level. In another embodiment of the present invention, the amount of data transfer varies depending on whether the soft or hard threshold is crossed.

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Fremont, CA, United States of America

Sriraman Chari