Advanced Micro Devices Corporation

Advanced Micro Device, Inc.

Sriram Srinivasan

William Louie Walker

Amitabh Mehra

Richard Martin Born

Xiaojie He

John Kelley

Michael L Golden

Gokul Subramani Ramalingam Lakshmi Devi

Matthew Schoenwald

Sneha Komatireddy

Xiuting Kaleen C Man

John Kalamatianos

Paul J Moyer

Jagadish B Kotra

Tarun Nakra

Patrick J Shyvers

Nicholas Dean Lance

An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.

Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches

A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

Transfer of cachelines in a processing system based on transfer costs

Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.

System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction

A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory including a plurality of entries, each entry storing state information for a corresponding cacheline of the first set of cachelines of one of the private caches.

Shadow tag memory to monitor state of cachelines at different cache level

A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.

Merging demand load requests with prefetch load requests

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Fort Collins, CO, United States of America

Sriram Srinivasan