International Business Machines Corporation

United Devices, Inc.

Prashtama Wireless LLC

Sriram Srinivasan Mandyam

Brian Walter O'Krafka

Robert James Ramirez

Edward A Hubbard

Ramanathan Raghavan

Brett Adam St Onge

Miwako Tokugawa

Archie Don Barrett, Jr

Jason Raymond Baumgartner

Kenneth Lee Wright

Jeffrey Thomas Kreulen

Krishnamurthy Venkatramani

David P Anderson

Shahram Salamian

Shubhada Saxena

A method for providing data conversion services is disclosed for a distributed processing system. The distributed processing system identifies and utilizes the capabilities of distributed devices connected together through a wide variety of communication systems and networks and utilize those capabilities to organize, manage and distribute project workloads to the distributed devices.

Data conversion services and associated distributed processing system

A massively distributed processing system and associated methods are disclosed that provide a processing architecture for utilizing a multitude of widely distributed devices to process distributed project workloads. To provide the processing infrastructure, a modular client agent program, which may include a system component and a separate project component, operates on the distributed devices to process workloads. For different projects, different project components may be provided to run on the base system component. In addition, a device capabilities database and an incentive database can be used by the server system to facilitate operations and encourage participation by client systems. Other databases may also be utilized to enhance system operations and functionality. And a wide variety of applications are possible, including network site testing, network site indexing, distributed data back-up, file sharing, data caching, data conversion, and scientific research, as well as many other distributed projects.

Massively distributed processing system with modular client agent and associated method

A security architecture and an associated method are disclosed for providing secure transmissions within distributed processing systems. More particularly, a server system is coupled to a network that is configured to be coupled to a plurality of distributed devices. The server system utilizes a security measure that is partitioned and distributed to multiple distributed devices. The distributed device receiving electronic information reconstructs the security measure by obtaining the various partitioned portions from the multiple distributed devices. In addition, the security measure may be generation of a hash value for the electronic information to be transmitted.

Security architecture for distributed processing systems and associated method

Apparatus and methods for dynamic simulation event triggering

One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory. Thereafter, a second sequence of values is read from the memory location and a window of observed values is defined, wherein the window has a highest observable value and a lowest observable value where the highest observable value is set to the highest value of the first sequence and the lowest observable value is set to the lowest value of the first sequence and wherein the lowest observable value is updated with a next observable value from the first sequence whenever the value of an individual read from the second sequence is higher than the lowest observable value so that a determination can be made whether individual values in the second sequence are within the window.

Hardware verification tool for multiprocessors

A method and system for implementing a network-based help architecture for software applications that reside on a host data processing system. A help database that is designed to support a software application that resides on a data processing system is integrated with an advanced knowledge base utilizing a standardized data format. The advanced knowledge base resides in a computer network to which the data processing system is linked. Next, and in response to selecting a help request associated with the software application, the help request is automatically converted into a data format readable by the computer network. Finally, the help database is dynamically supplemented and updated utilizing the advanced knowledge base, such that, in response to the step of selecting a help request associated with the software application, seamless access is provided within the computer network to the help database and the advanced knowledge base.

Network-based help architecture

A multiprocessor data processing system includes a shared main memory and a plurality of processors connected to the memory utilizing a system bus. Data is transferred utilizing the system bus. The plurality of processors include a first processor and a second processor. The first processor includes a first cache, and the second processor includes a second cache. The multiprocessor data processing system executes a test program. During execution of the test program, a first and a second trace are generated. The first trace is generated by monitoring all events occurring at a first location within the system. The second trace is generated by monitoring all events occurring at a second location within the system. Each event is associated with a time of occurrence of that event. The first trace includes each event which was monitored at the first location and the time associated with each event. The second trace includes each event which was monitored at the second location and the time associated with each event. The first and second traces are stored and utilized to determine if the multiprocessor data processing system is operating correctly.

Method and system for testing a multiprocessor data processing system

One aspect of the invention relates to a method for detecting synchronization violations in a multiprocessor computer system having a memory location which controls access to a portion of memory shared by the processors, the memory location having at least one lock bit indicating whether the portion of memory is locked by one of the processors and a plurality of bits for storing a data value. The method comprises reading the memory location by an individual processor; testing the lock bit to determine whether the portion of memory is locked; if the portion of memory is not locked; asserting the lock bit to indicate the portion of memory is locked; incrementing the data value to represent a global access count; writing the lock bit and the data value back to the memory location; and incrementing a data value stored in a memory location associated with the individual processor to indicate an individual access count by the individual processor. The individual access counts for each processor are then summed and compared to the global access count to determine whether a synchronization violation has occurred.

A method and apparatus for creating a multiprocessor verification environment. A Multiprocessor Test Generator (MPTG) generates a set of test cases in a Multiprocessor Test Language (MTL) format subject to constraints and enumeration controls in a test specification. An abstract system model of the machine under test is inputted to the Multiprocessor Test Generator. The Multiprocessor Test Generator (MPTG) receives the test specification and abstract system model, accesses a system specific database and generates test cases based on the constraints in the test specification in a Multiprocessor Test Language (MTL). The Multiprocessor Test Language (MTL) test cases are inputted to a Multiprocessor Test Executive (MPX) which controls the issuance of the test cases to a cache-coherent multiprocessor system, and monitors their completion in order to verify operation of the cache-coherent multiprocessor system.

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Austin, TX, United States of America

Sriram Srinivasan Mandyam