Intel Corporation

Sriram Srinivasan

Ram S Viswanath

Debendra Mallik

Brent M Roberts

Mihir K Roy

Robert L Sankman

Ravindranath Vithal Mahajan

Rajat Agarwal

Dheeraj R Subbareddy

Ravi Prakash Gutala

Scott J Weber

Md Altaf Hossain

Ankireddy Nalamalpu

Rajasekaran Swaminathan

Amruthavalli Pallavi Alur

Aravind Raghavendra Dasu

Sandeep B Sane

Mark T Bohr

John Stephen Guzek

William J Lambert

Kaladhar Radhakrishnan

Krishna Bharath

Sairam Agraharam

Joshua Heppner

Leonel R Arana

Carl L Deppisch

Cengiz Ahmet Palanduz

Wei-Lun Kane Jen

Andrew W Yeoh

Michael J Hill

Sri Chaitra Jyotsna Chavali

Deepak Kulkarni

Gregorio R Murtagian

Rajen S Sidhu

Victor Prokofiev

Paul R Start

Gregory S Constable

Joel A Auernheimer

Sridhar Narasimhan

Bhanu Jaiswal

Adel A Elsherbini

Kemal Aygun

Zhiguo Qian

Zhichao Zhang

Mathew J Manusharow

Sanka Ganesan

Wilfred Gomes

Jeffory L Smalley

Ralph V Miele

Srikant Nekkanty

Richard J Dischler

Thomas A Boyd

Yidnekachew S Mekonnen

Jeff C Morriss

Christopher Schaef

Kuang C Liu

Huong T Do

Steven A Klein

Eric W Buddrius

Yu Amos Zhang

Eduard Roytman

Shelby A Ferguson

Zhe Chen

Luis Gil Rangel

Muffadal Mukadem

Francis Toth, Jr

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Interconnect architecture with silicon interposer and EMIB

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Packaging architecture for disaggregated integrated voltage regulators

Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

Differential crosstalk self-cancelation in stackable structures

An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

Via-in-via structure for high density package integrated inductor

An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

Asymmetric electronic substrate and method of manufacture

Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

Rlink&#x2014;die to die channel interconnect configurations to improve signaling

An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.

Electronic device, socket, and spacer to alter socket profile

Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Methods of fabricating low melting point solder reinforced sealant and structures formed thereby

An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element.

Vertical socket contact with flat force response

Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Method of forming a substrate core with embedded capacitor and structures formed thereby

A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.

Mechanism for facilitating and employing a magnetic grid array

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Methods of forming ultra thin package structures including low temperature solder and structures formed therby

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Chandler, AZ, United States of America

Sriram Srinivasan