Intel Corporation

Sriram R Vangal

Vivek K De

Krishnan Ravichandran

Nitin Y Borkar

Yatin Hoskote

Turbo Majumder

Dinesh Somasekhar

Harish Krishnamurthy

Vaibhav Vaidya

Christopher Schaef

Nachiket Venkappayya Desai

Suhwan Kim

Xiaosen Liu

Khondker Z Ahmed

Vasantha K Erraguntla

Shekhar Yeshwant Borkar

Jianping Xu

Jayanth Mallanayakanahalli Devaraju

Miguel Bautista Gabriel

Tanay Karnik

James W Tschanz

Stephen H Gunther

Somnath Paul

Robert Milstrey

Howard A Wilson

Ram K Krishnamurthy

Muhammad M Khellah

Narayan Srinivasa

Jawad Basit Khan

Stephen R Mooney

Rajesh Sundaram

Shigeki Tomishima

Pratik A Patel

Steven Hsu

Srikanth T Srinivasan

Matthew B Haycock

Patrick Koeberl

Carlos Alfonso Tokunaga

Chetan Chauhan

Zhen Fang

Vinayak Honkote

Amaresh Pangal

Eugene M Kishinevsky

Suyoung Bang

Stephen Kim

Farzin Guilak

Liqun Cheng

Bhaskar P Chatterjee

Saurabh Dighe

Michael Abbott

Venkat S Veeramachaneni

Sunghyun Park

Arvind Pratap Singh

Hyochan An

Pratik Dasharathkumar Patel

Miguel Mario Bautista Gabriel

An integrated circuit (IC) is provided for in-situ anomaly detection. Sensors in the IC generates sensor datasets including information indicating conditions in the IC. A processing unit in the IC uses a sensor dataset and a model to detect and classify the anomaly. The processing unit may filter the sensor dataset, extract features from the filtered sensor dataset, and input the features into the model. The model outputs one or more classifications of the anomaly. A feature may be a distance vector that represents a difference between a data value in the filtered sensor dataset from a reference data value. The model may be a network of bit-cells in the IC. The model may be continuously trained in-situ, i.e., on the IC. The processing unit may provide the classifications to another processing unit in the IC. The other processing unit may mitigate the anomaly based on the classifications.

In-situ detection of anomalies in integrated circuits using machine learning models

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

Circuits and methods for supply voltage detection and timing monitoring

A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

Circuits and methods for voltage detection in integrated circuits

In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

Multiple output voltage conversion

Circuitry is provided to control a performance level of a processing device depending on two or more operating points of the processing device. An operating point has a corresponding frequency and a corresponding voltage. The performance-level control circuitry arranged to cross-multiply parameters corresponding to a first operating point and a second, different operating point of the processing device. A relative energy expenditure of the first operating point and the second operating point is determined based on the cross multiplication. An operating point of the processing device is selected depending on the determined relative energy expenditure. An apparatus having the performance level control circuitry, machine readable instructions for implementing the performance level control and a corresponding method are also provided.

Controlling a processing performance level depending on energy expenditure

In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.

Energy harvester with multiple-input multiple-output switched-capacitor (MIMOSC) circuitry

Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

Physically unclonable function implemented with spin orbit coupling based magnetic memory

Various embodiments of the invention may be used to find a combination of voltage and frequency that results in a minimum amount of energy consumption in a digital system, including energy consumed by the system's voltage regulator (VR). The process may involve finding a separate point of minimum energy consumption for each of several different modes of the VR, where a mode is the ratio of Vin to Vout for that VR. The smallest value of those points may then be selected as the overall minimum. The process for making this determination may be performed in situ while the device is in operation, and may encompass changes in operational temperature, load, and process variations.

Voltage regulator efficiency-aware global-minimum energy tracking

Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

Peak-delivered-power circuit for a voltage regulator

Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.

Vretention detector apparatus and method

Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

Master-slave controller architecture

Some embodiments include apparatuses and methods having a power switching unit to receive a first voltage and provide a second voltage having a value based on a value of the first voltage, a first loop to provide digital control information to control a switching of the power switching unit in order to maintain a relationship between the value of the second voltage and a value of a reference voltage, and a second loop coupled to the power switching unit and the first loop to calculate a value of energy consumption of at least a portion of the apparatus based at least on the digital control information.

Digital low drop-out voltage controller including embedded dual-loop feedback for minimum energy point operation

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Growing community of inventors

Hillsboro, OR, United States of America

Sriram R Vangal