Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Intel Ndtm US LLC

Sriram Natarajan

Shankar Natarajan

Suresh Nagarajan

Arun Sitaram Athreya

Yihua Zhang

Romesh B Trivedi

Ramkarthik Ganesan

Arun Athreya

Shivashekar Muralishankar

Rohit Sudhir Shenoy

Jason B Akers

Hinesh K Shah

Orapin Yoder

Venkata S Surampudi

Grzegorz Kowalczyk

Parth Donga

A system and related method, the system including control circuitry and memory with a first memory block of a first memory density and a second memory block of a second memory density which is greater than the first memory density. Control circuitry, which is communicatively coupled to the memory, is configured to determine to transfer data from the first memory block to the second memory block, generate parity data based on the data and cause to store the parity data at a parity address corresponding to an available portion of the first memory block. Control circuitry is further to cause to update a look-up table with the parity data address and cause to copy the data from the first memory block to the second memory block.

Flexible raid parity application for memory management

A system and related method, including memory and processing circuitry, which is to write data of a data stream. The memory includes a first memory portion of a first density and a second memory portion of a second density. The processing circuitry receives a write request. The processing circuitry is then to select to write the data to the first memory portion based on a characteristic of the data stream, wherein both the first memory portion and the second memory portion are available to be written to, and the processing circuitry then causes the data to be written to the first memory portion. The processing circuitry may select to write the data to the first memory portion based on a size of the data stream and/or based on a bandwidth of writing data of the data stream to the memory.

Host bandwidth optimized data stream memory writes

This application is directed to memory management in an electronic device. A memory includes a plurality of superblocks and receives a plurality of access requests. The electronic device stores information of an ordered list of superblocks in a cache, and each of a first subset of superblocks has a hint value and is ordered based on the hint value. In response to the plurality of access requests, the electronic device accumulates respective hint values of the first subset of superblocks and dynamically determines positions of the first subset of superblocks in the ordered list of superblocks based on the respective hint values of the first subset of superblocks. The ordered list of superblocks is pruned to generate a pruned list of superblocks. Based on the pruned list of superblocks, the electronic device converts a second subset of superblocks from a first memory type to a second memory type.

Firmware management of least recently used memory for cache hint optimization

This application is directed to data protection in a memory system of an electronic device. The memory system has a first memory block and a second memory block, and each memory block includes one or more respective memory dies. Each memory die of the second memory block is distinct from the one or more respective memory dies of the first memory block. The electronic device stores user data including a plurality of user data items in the first memory block and integrity data including a plurality of integrity data items in the second memory block. Each of the plurality of user data items is configured to be validated based on a respective one of the plurality of integrity data items. The electronic device invalidates the integrity data in the second memory block, and reads the user data from the first memory block independently of the integrity data.

Controlling memory overhead for storing integrity data in solid state drives

In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Techniques for preventing read disturb in NAND memory

Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.

System approach to reduce stable threshold voltage (Vt) read disturb degradation

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.

Detection and error-handling of high error rate blocks during copyback

An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

Dynamic single level cell memory controller

An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.

Mass storage device with host initiated buffer flushing

Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Block management for dynamic single-level cell buffers in storage devices

Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.

Growing community of inventors

Folsom, CA, United States of America

Sriram Natarajan