Texas Instruments Corporation

Sriram Narayanan

Srinath Mathur Ramaswamy

Ajit Sharma

Arup Polley

Seung Bae Lee

Marco Corsi

Leonardo William Estevez

David Louis Freeman

Jian Jim Wang

Thanh Thien Tran

Gangadhar Burra

Russell Melvin Rosenquist

Wen Li

Jonathan Edward Hunter

A sensor power management arrangement includes a signal processing circuit configured to receive signal from a sensor, to test the signal against at least one criterion, and to pass the signal for further processing in response to the signal passing the at least one criterion. In this way, only signals that are of a sufficient importance or significance will consume the maximum amount of processing energy and through processing by later processes or circuitry. Should a signal from a sensor not be strong enough or meet other criteria, power will not be wasted in preparing that signal for provision to the microcontroller or microprocessor. Additional flexibility in the sensor power management can be realized by adjusting the criteria against which the sensor signal is compared based on a status of the sensor apparatus.

Sensor power management

An LED (light-emitting diode) driver for a photoplethysmography system, including a switched-mode operational amplifier for driving a driver transistor with a source-drain path in series with the LED. In a first clock phase in which the LED is disconnected from the driver transistor, the amplifier is coupled in unity gain mode, and a sampling capacitor stores a voltage corresponding to the offset and flicker noise of the amplifier; the gate of the driver transistor is precharged to a reference voltage in this first clock phase. In a second clock phase, the sampled voltage at the capacitor is subtracted from the reference voltage applied to the amplifier input, so that the LED drive is adjusted according to the sampled noise. A signal from the transmitter channel is forwarded to a noise/ripple remover in the receiving channel, to remove transmitter noise from the received signal.

Transmitter architecture for photoplethysmography systems

An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier.

Baseline compensation system

A network of sensor and controller nodes having the ability to be dynamically programmed and receive updated software from one another, and from a host system. Each network node includes multiple state machines, at least some of which are operable relative to physical pins at the network node; the physical pins correspond to inputs from sensor functions or outputs to control functions. The network nodes include microcontrollers that are operable in an operating mode to execute a state machine and respond to commands from other nodes or the host, and in a read mode to receive and store program instructions transmitted from other nodes or the host. A learn mode is also provided, by way of which a network node can store program code corresponding to instructions and actions at the node when under user control.

Network node physical/communication pins, state machines, interpreter and executor circuitry

A periphery band is around an excluded region. For automatically counting physical objects within the periphery band and the excluded region, an imaging sensor captures: a first image of the periphery band and the excluded region; and a second image of the periphery band and the excluded region. In response to the first image, a first number is counted of physical objects within the periphery band and the excluded region. Relevant motion is automatically detected within the periphery band, while ignoring motion within the excluded region. In response to the second image, a second number is counted of physical objects within the periphery band and the excluded region. In response to determining that a discrepancy exists between the detected relevant motion and the second number, the discrepancy is handled.

Method and system for automatically counting physical objects within a periphery band and an excluded region

The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.

Optical receiver chain for components of a photoplethysmograph signal

Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.

Methods and apparatus for reducing noise, power and settling time in multi-modal analog multiplexed data acquisition systems

An optical system includes an optical illumination source, an optical receiver, a correlation determination circuit, and an ambient condition control circuit. The optical illumination source is configured to emit a light in the direction of a target object. The optical receiver is configured to receive a combined optical signal that includes an ambient light component combined with an interrogation component. The correlation determination circuit is configured to compare the combined optical signal with an ambient light signal to identify a correlation factor. The ambient condition control circuit is configured to compare the correlation factor to a low correlation threshold value and a high correlation threshold value, and, based on the correlation factor exceeding the low threshold value and being less than the high correlation threshold value, cancel the ambient light component from the combined optical signal to produce an interrogation signal including the interrogation component.

Exploiting constructive interference from ambient conditions

A method of synchronizing includes providing a sensor network including sensor nodes having object recognition sensors (ORS's) and building automation network nodes. The ORS's have partially overlapping fields of view in a sensed overlap area in the building. Movement of an individual through the sensed overlap area triggers dynamic synchronizing with the first sensor node waking up and sending a first RF request to join a subnet and for a schedule of wakeup times, the first sensor node receiving a response from any sensor node that receives the first request including synchronization information having times the first sensor node should wake up. The second sensor node is activated by the individual's movement and sends a second RF message to join the subnet and for a schedule of wakeup times. The first sensor node receives the second RF message and in response sends the synchronization information to the second sensor node.

Sensor synchronized networks using overlapping sensor fields

A computing device () includes a storage () that over time is operable to include video and graphics content and the storage has a first set of instructions representing lossy video compression () and a second set of instructions representing lossless compression (); and a processor () coupled with said storage (), and said processor () operable to electronically analyze () at least a portion of the content for motion based on magnitudes of motion vectors and, on detection of a significant amount of motion, further operable to activate the first set of instructions () to compress at least the motion video, and otherwise to activate the second set of instructions representing lossless compression () to compress at least the graphics. Other devices, systems, and processes are disclosed.

Hybrid video and graphics system with automatic content detection process, and other circuits, processes, and systems

Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input signal, an analog detector circuit to provide a detector output signal representing a feature of the input signal, a second sampling circuit to sample the detector output signal, and a control circuit to control a sample rate or other analog front end operating parameter at least partially according to the sampled detector output signal, and to selectively enable and disable the analog detector circuit at least partially according to a model representing an expected repeating waveform of the input signal.

Sensor with low power model based feature extractor

The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) () is substantially reduced by using a number of shared capacitors (SC-SCs&#x2212;1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.

Calibrated SAR ADC having a reduced size

An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.

Dual comparator-based error correction scheme for analog-to-digital converters

A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a signal at a sampling rate that is dynamically variable by the digital circuit based on the bandwidth of the incoming signal. The digital circuit is to automatically assert a signal to the analog circuit to change a bias current of the analog circuit based on a change to the sampling rate in the digital circuit.

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Richardson, TX, United States of America

Sriram Narayanan