Qualcomm Incorporated

Cisco Technology, Inc.

Sriram Narayan

Subrahmanyam Dravida

Denis Claveloux

Mark S Wallace

Shailesh Maheshwari

Jay Rodney Walton

Marcello Vincenzo Lioy

Thomas Klingenbrunn

Uppinder Singh Babbar

Dev Vrat Gupta

Franklin Peter Antonio

Vanitha Aravamudhan Kumar

Jean-Marie Tran

Gurvinder Singh Chhabra

Idreas Mir

Irfan Anwar Khan

Wei Ye

Samson Jim

Mathias Kohlenz

Anthony Monteiro

Vikas Nagpal

Paiman Nodoushani

Vikram Saksena

Kyung-Yeop Hong

David S Yoon

Subra Dravida

Shailesh Maheswari

Irfan A Khan

Jean-Marie Qd Tran

Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.

Hardware acceleration for WWAN technologies

Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. Various other aspects are also presented.

Memory management for high speed media access control

Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.

A power-efficient wireless device is equipped with multiple (N) antennas. Each antenna is associated with a transmitter unit and a receiver unit. The wireless device also has processing units used to perform various digital processing tasks. The transmitter units, receiver units, and processing units may be selectively enabled or disabled. In an idle state, the wireless device may enable only a subset (e.g., one) of the N receiver units and one or few processing units for signal detection and acquisition. For active communication, the wireless device may enable Ntransmitter units for data transmission and/or Nreceiver units for data reception, where 1&#x2266;N&#x2266;N and 1&#x2266;N&#x2266;N. The enabled processing units may also be clocked at a lower frequency whenever data is transmitted or received at a data rate lower than the highest data rate. The wireless device may go to sleep whenever possible to conserve power.

Power-efficient multi-antenna wireless device

A loop carrier system includes a home local area network having plural telephone modules and a hub coupled to in-home telephone wiring. The telephone modules and the hub communicate voice signals over the in-home wiring in a dedicated frequency band above baseband POTS. The hub converts between voice signals and voice packets and is connected to a network access device for transferring the voice packets from the home local area network to a telecommunications network which routes the voice packets to a gateway. The gateway converts between the voice packets and a circuit format compatible with a local digital voice switch. The home local area network includes a timing recovery mechanism which in the absence of a clock that is traceable to the Primary Reference Clock on the public network is robust to clock drift, cell delay variation and cell impairments.

Virtual loop carrier system with network clock recovery

A loop carrier system includes a home local area network having plural telephone modules and a hub coupled to in-home telephone wiring. The telephone modules and the hub communicate voice signals over the in-home wiring in a dedicated frequency band above baseband POTS. The hub converts between voice signals and voice packets and is connected to a network access device for transferring the voice packets from the home local area network to a telecommunications network which routes the voice packets to a gateway. The gateway converts between the voice packets and a circuit format compatible with a local digital voice switch.

Virtual loop carrier system

Growing community of inventors

Westford, MA, United States of America

Sriram Narayan