Globalfoundries Inc.

Advanced Micro Devices Corporation

Globalfoundaries Inc.

Sriram Madhavan

Shobhit Malik

Luigi Capodieci

Darin A Chan

Jung-Suk Goo

Qiang Chen

Uwe Paul Schroeder

Piyush Pathak

Lynn Wang

Andrew Evert Carlson

Robert C Pack

Wei-Long Wang

Swamy Muddu

Biju Parameshwaran

Karthik Krishnamoorthy

Thomas Herrmann

Eric Chiu

Fadi S Batarseh

Lynn Tao-Ning Wang

Shikha Somani

Stefan Schüler

An IC design layout is decomposed into multiple masks to produce an initial output. A post-decomposition optimization is performed. The post-decomposition optimization includes identifying hotspots in the multiple masks, clustering features that contribute to the hotspots into clusters, identifying ones of the clusters that can be relocated to a different mask to eliminate the hotspot, without violating design rules, as reversible clusters, ranking movement of the reversible clusters by comparing the reversible clusters, as potentially moved, to known manufacturability metrics, and moving the reversible clusters to different masks according to the priority established by the ranking, to produce a post-decomposition optimized tape-out. The IC devices are manufactured by applying the post-decomposition optimized tape-out to manufacturing equipment.

IC layout post-decomposition mask allocation optimization

A method and apparatus for selecting Si wafer WP based on individual or multiple DFM decks for Si-feed-forward and Si-feed-back analysis are provided. Embodiments include generating markers for a wafer from an individual DFM deck; generating UCF Indexes; determining whether a representative marker corresponding to a UCF is a candidate for WP prediction; extracting markers corresponding to that UCF-Index (UEF data) from a candidate; performing a UCF-Index-based sampling on the extracted UEF data set if a number of markers in the extracted UEF data set is larger than an inspection requirement; adding a location of each marker or group of markers in the extracted UEF data set to a sitelist after the UCF-Index-based sampling; sending the sitelist to a foundry for metrology analysis on sitelist locations; and adding the sitelist locations and corresponding UCF Index and metrology parameters to a design analysis database for analyzing other wafers/UCF Indexes.

Feed-forward for silicon inspections (DFM2CFM : design to silicon) and feed-back for weakpoint predictor decks (CFM2DFM : silicon to design) guided by marker classification, sampling, and higher dimensional analysis

Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.

Method, system and program product for identifying anomalies in integrated circuit design layouts

Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.

Stitch insertion for reducing color density differences in double patterning technology (DPT)

An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.

Method and apparatus for applying post graphic data system stream enhancements

A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. Outer markers are generated in the computing apparatus for at least a subset of the features based on the proximity of the features to one another and spacing requirements. Features are identified in the computing apparatus where the associated outer marker has at least one dimension greater than the dimensions specified for the feature.

Pattern based method for identifying design for manufacturing improvement in a semiconductor device

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts

A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Body tie test structure for accurate body effect measurement

According to one exemplary embodiment, a test device includes a transistor situated on a substrate. The test device further includes a protection device coupled by a fuse to a gate of the transistor in an interconnect metal layer, where the interconnect metal layer is formed over the substrate. The fuse allows the protection device to be decoupled from the gate of the transistor prior to testing the transistor. The test device further includes first and second contact pads formed over the substrate and coupled to respective terminals of the fuse to provide access to the fuse. A current can be applied between the first and second contacts pads to cause the fuse to open to decouple the protection device from the gate of the transistor. The test device further includes an antenna coupled to the gate of the transistor with interconnect metal segments for accumulating electrical charge during wafer processing.

Growing community of inventors

Santa Clara, CA, United States of America

Sriram Madhavan