Globalfoundries Inc.

Sriram Balasubramanian

Vivek Joshi

Randy W Mann

Kevin J Yang

William McMahon

Zhi-Yuan Wu

Yoann Mamy Randriamihaja

Chad Weintraub

Lingquan Wang

Juhi Bansal

Ratheesh Ramachandran Thankalekshmi

Vineet Wason

Karthik Chandrasekaran

Varsha Balakrishnan

Arunima Dasgupta

A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Method to identify extrinsic SRAM bits for failure analysis based on fail count voltage response

At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for providing a dual port memory device. An inline DC contention margin test is performed for testing a contention margin related to a write operation into a cell of the memory device. A determination is made as to whether the contention margin is within a predetermined range. A responsive action is performed in response to determining that the contention margin is outside the predetermined range.

Methods, apparatus and system determining dual port DC contention margin

Worst case performance of an SRAM cell may be simulated more accurately with less intensive computations. An embodiment includes determining, by a processor, a process corner G of an SRAM cell, having pull-down, pass-gate, and pull-up devices, process corner G being defined as the worst performance of the cell when only global variations of parameters of the SRAM cell are included, setting each of the pull-down, pass-gate, and pull-up devices at process corner G, performing, on the processor, a number of Monte Carlo simulations of the SRAM cell devices around process corner G with only local variations of the parameters, generating a normal probability distribution for Ibased on the local Monte Carlo simulations around process corner G, extrapolating the worst case Ifrom the normal probability distribution of Ito define a process corner SRM representing a slowest SRAM bit on a chip, and validating an SRAM cell based on the SRM corner. Embodiments further include creating a library of SRM corner values for multiple SRAM cells, and validating an SRAM cell by selecting an SRM corner from the library. Embodiments further include linearly scaling the SRM corner value with global sigma input variations from 0 sigma to 6 sigma and/or with local sigma input variations from 0 sigma to 6 sigma, selecting a scaled SRM corner value at the sigma corresponding to design and memory size requirements for the SRAM cell, simulating the scaled SRM corner by a processor, and employing the simulated scaled SRM corner to validate performance of an SRAM cell.

Model library implementation and methodology for worst case performance modeling for SRAM cells

MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. With the gate stack serving as a mask, impurity dopants are implanted into a semiconductor material having a first surface and disposed proximate to the gate stack. A trench is etched into the semiconductor material such that the semiconductor material has a trench surface within the trench. Further, a metal silicide layer is formed on the first surface of the semiconductor material and on the trench surface. Also, a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface is fabricated.

MOS structures that exhibit lower contact resistance and methods for fabricating the same

MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated.

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Fremont, CA, United States of America

Sriram Balasubramanian