Intel Corporation

Srinivasan T Rajappa

Romesh B Trivedi

Zohar Bogin

Serafin E Garcia

Rajagopal Subramanian

Robert J Johnston

Girish P Ramanathan

A system for measuring timing margins in an interface between a core and an input/output device on a chipset. In order to measure the amount of available variation in data and strobe signals, delay lines are introduced so that the data and strobe signals may be varied in relation to each other. By incrementally changing the delay and hence the time difference between the two signals, it is possible to determine the allowable variation when the device fails to operate. By providing delays on both sides, it is possible to determine the timing margin on both the setup and hold of the signals.

System for varying timing between source and data signals in a source synchronous interface

A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.

A glitch detection circuit is described for detecting a glitch on a strobe signal transmitted over a single strobe interface. The glitch detection circuit includes a first input terminal to receive a single strobe signal and a second input terminal to receive a protocol control signal. The glitch detection circuit uses a double edge detection circuit to detect two consecutive rising or falling edges on the strobe signal. The double edge detection circuit becomes initialized by an initializing circuit each time the logical state of the control signal changes from a first state to a second state. The glitch detection circuit is configured to output a glitch detection signal when two consecutive rising or falling edges are detected by the double edge detection circuit before being initialized by the initializing circuit.

Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal

The present invention is a method and apparatus to generate first and second strobe signals to receive data on an interface port of a processor operating in first and second modes at first and second voltage levels, respectively. The second voltage level is higher than the first voltage level. A selector provides first and second selected signals from a plurality of signals which corresponds to the first and second modes. The selector operates at the second voltage level. A signal generator is coupled to the selector to generate the first and second strobe signals from the first and second selected signals.

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Folsom, CA, United States of America

Srinivasan T Rajappa