Western Digital Technologies, Inc.

Srinivasan Seetharaman

Sourabh Sankule

Piyush Girish Sagdeo

Gautam Ashok Dusija

Chris Yip

Chris Nga Yee Yip

The disclosure relates in some aspects to a design for a data storage apparatus with a non-volatile memory that includes a block of memory comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a failure in a first sub-block. The second sub-block is then marked, in response to a failure detection in the first sub-block, with an initial designation as an unusable sub-block, and a test of the second sub-block is performed to determine a usability of the second sub-block. Based on the test, the second sub-block is then marked with a second designation that is one of a tested usable sub-block or a tested unusable sub-block.

Systems and methods for evaluating integrity of adjacent sub blocks of data storage apparatuses

The disclosure relates in some aspects to a read scrub design for a non-volatile memory that includes a block comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a trigger event associated with a read command performed on the first sub-block. A target sub-block test is then performed in response to a detection of the trigger event to determine whether to add the first sub-block to a read scrub queue. If the first sub-block is added to the read scrub queue, a sister sub-block test is then performed to determine whether to add the second sub-block to the read scrub queue.

Sub block mode read scrub design for non-volatile memory

Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.

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Milpitas, CA, United States of America

Srinivasan Seetharaman