International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Srinivasan Ramani

Ken Van Vu

Rohit Taneja

Ganesh Balakrishnan

Brian Michael Rogers

Michael Stephen Floyd

Malcolm Scott Allen-Ware

Mohammad Peyravian

Karthick Rajamani

Todd Jon Rosedahl

Anil Krishna

Tejas S Karkhanis

Gordon Bernard Bell

Pradip Bose

Gordon Taylor Davis

Thuong Quang Truong

Eric Francis Robinson

Charles Francis Marino

Gregory Scott Still

Heather Lynn Hanson

Etai Adar

Srinivas Bangalore Purushotham

Kirk David Peterson

Brian William Thompto

Malcolm Scott Ware

Charles Robert Lefurgy

Jeffrey Haskell Derby

Prasanna Jayaraman

Victor V Zyuban

Bishop Chapman Brock

Joshua D Friedrich

David John Palframan

Erika Gunadi

Nan Ni

Swapnil Shah

Steve Woolet

John Steven Dodson

Alper Buyuktosunoglu

Clark Debs Jeffries

Hans Mikael Jacobson

Russell Dean Hoover

Kenneth Lee Wright

Chen-Yong Cher

David John Krolak

Dongming Hwang

Augusto Javier Vega

Jordan Ross Keuseman

Jeffrey Powers Bradford

Kartik Sudeep

Sooraj R Nair

Chen Yong Cher

Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. The processor defines a special store instruction that is different from a regular store instruction. The special store instruction is used in regions of the computer program where memory aliasing may occur. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing may occur.

Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur

Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Managing servers with quality of service assurances

Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.

Processor that detects memory aliasing in hardware and assures correct operation when memory aliasing occurs

A primary interval for convergence of at least one power series in a transcendental function is interpolated, while selecting a number of one or more interpolation points for a truncated expansion of the at least one power series by a selected order of truncation. A function and at least one derivative of the function of the truncated expansion of the selected order of truncation is evaluated at the one or more interpolation points. Each separate value evaluated for the function and each of the at least one derivative is saved in a table, wherein the table is looked up for efficiently computing a result of the truncated expansion of the at least one power series.

Power series truncation using constant tables for function interpolation in transcendental functions

Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The compiled code is then executed on the processor hardware, which detects memory aliasing at run-time and assures proper operation of the code even when memory aliasing occurs.

Performing register promotion optimizations in a computer program in regions where memory aliasing may occur and executing the computer program on processor hardware that detects memory aliasing

Compiler that performs register promotion optimizations in regions of code where memory aliasing may occur

A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Virtual power management multiprocessor system simulation

A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Deterministic current based frequency optimization of processor chip

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Cary, NC, United States of America

Srinivasan Ramani