Intel Corporation

Srinivasan Rajagopalan

Alexander Levin

Nazar Syed Haider

Fern Nee Tan

Sanjiv Soman

Cau L Nguyen

An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.

Isolation module for use between power rails in an integrated circuit

A method and apparatus is presented that can provide first and second windows for driving data onto a bus in dependence on bus clock frequency. In one example, the speed of the bus clock is determined by a component such as a processor. If the bus clock frequency is at a first, relatively high frequency, data is driven onto the bus in an earlier time window (e.g., near the rising edge of the bus clock signal). If the bus clock frequency is at a second, lower frequency, data is driven onto the bus in a second, later time window (e.g., near the center of the high level of the bus clock). Accordingly, the time window for receiving the data driven onto the bus need not be changed (e.g., near the rising edge of the next bus clock signal) allowing components to work effectively with both bus clock frequencies.

Method and apparatus for controlling bus transactions depending on bus clock frequency

Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Slew rate control circuit

A circuit for driving GTL-type buses actively drives a bus trace towards a first reference voltage when a signal in a first voltage state is detected at its input and actively drives the bus trace towards a second reference voltage for a selected period when the signal at its input transitions from the first voltage state to a second voltage state. The circuit includes a flip-flop for storing the sequential voltage states of the signal, logic for comparing the current voltage state of the signal with a replica of the preceding voltage state of the signal, and first and second transistors of complementary conductivity types, for driving the bus trace to first or second reference voltages, respectively, when activated. The first transistor is turned on when the signal is in the first voltage state. The second transistor is turned on for a period determined by the clock signal driving the flip flop, the type of flip-flop, and, optionally, additional logic gates, when the signal transitions from the first voltage state to the second voltage state.

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Palo Alto, CA, United States of America

Srinivasan Rajagopalan