Bay Microsystems, Inc.

Intel Corporation

Srinivasan Murari

Heena Nandu

Pradeep Shrikrishna Limaye

Piers John Daniell

A telecommunications network node architecture is disclosed that enables a telecommunications network that uses automatic protection switching to be expanded to include more nodes than its standard protocol provides for without modifying the standard protocol or the existing nodes in the network. Although the illustrative embodiment is depicted as using the SONET/SDH protocol, it will be clear to those skilled in the art, after reading this specification, how to make and use embodiments of the present invention that use automatic protection switching with another protocol. The illustrative embodiment comprises: an automatic protection switching channel that defines an address space in the telecommunications network; a node that is uniquely identified by an address in the address space; and a node that is not uniquely identified by an address in the address space.

Expansion of telecommunications networks with automatic protection switching

An apparatus and method that extend the automatic protection switching protocol to address at least 256 network nodes. By using overhead bytes as extended APS node IDs, large single ring SONET/SDH systems can be avoided. This means APS messages that force every node into a single ring can be avoided and recovery performance from a break in the ring or a node fault can be improved. The protocol for the extended automatic protection switching channels takes multiple extended APS node IDs from tributary lines and merges those extended APS ID's into a single SONET/SDH stream on another line. Placement of the extended APS node ID's in the overhead bytes of SONET/SDH frames allows easy relay around each SONET/SDH ring.

Multiplexed automatic protection switching channels

A method and apparatus for emulating status flags on a computer system that has no native support for status flags. One embodiment of the invention includes decoding an arithmetic instruction executable on a first Instruction Set Architecture (ISA), wherein the instructions generates at least one status flag when executed on the first ISA. The arithmetic instruction is translated to be executable on a second ISA. When executed on the second ISA, the translated arithmetic instruction generates a first intermediate result by performing a first logical exclusive-or (XOR) operation between a first operand and a second operand. The arithmetic instruction then generates a first final result by performing a second XOR operation between the first intermediate result and an arithmetic result, which was generated by an arithmetic operation specified by the arithmetic instruction. As a result, the first final result has at least one bit representing a status flag of the arithmetic result.

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Fremont, CA, United States of America

Srinivasan Murari