Arm Limited

Koninklijke Philips Corporation N.V.

Silicon Hive B.v.

Srinivasan Balakrishnan

Carlos Antonio Alba Pinto

Harm Johannes Antonius Maria Peters

Ramanathan Sethuraman

Aleksandar Beric

Patrick Peter Elizabeth Meuwissen

Rafael Peset Llopis

Gerard Veldman

Ramanathan Setheraman

Venkata Niranjan Cherukuri

Chirumamilla Lakshmana Rao

Various implementations described herein are related to a device having sensing circuitry that receives an input signal and provides an output signal based on sensing a resistance differential between multiple shield resistors or based on sensing a change in voltage across a shield wire of a shield wiring network. The device includes comparing circuitry that receives the output signal and provides an alarm signal based on detecting a tampering event associated with the resistance differential or the change in voltage.

Tamper detection techniques

A power distribution circuit can include a comparator circuit that is formed of an inverter. The inverter can be configured with a trip voltage value (Vtrip) different than half a supply voltage value (VDD/2) for further energy efficiencies in discharging a charge storage device used in the power distribution circuit to gain security.

Energy efficient power distribution circuits for protection of sensitive information

An array of data values, such as an image of pixel values, is stored in a main memory (). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region () of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations () is performed. Locations that store pixel data for locations in the image outside the region () are selected for replacement, selectively exempting from replacement cache locations () that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region. In a further embodiment the cache for locations inside the region contains sets of banks, each set for a respective line from the image, data from the lines being distributed in a cyclically repeating fashion over the banks.

Data processing apparatus that provides parallel access to multi-dimensional array of data values

A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

Data processing apparatus with parallel operating functional units

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Bengaluru, India

Srinivasan Balakrishnan