Sandisk Technologies Inc.

Srinivasa Rao Sabbineni

Bhavin Odedara

Deepak Pancholi

Jayaprakash Naradasi

Jayanth Mysore Thimmaiah

Srikanth Bojja

Naidu Prasad

Shiv Harit Mathur

Anand Venkitachalam

Sateesh Desireddi

Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.

Space and power-saving multiple output regulation circuitry

An electronic device may receive a supply voltage from another external device, and detect when a level of the supply voltage drops below a threshold. In response, a controller of the electronic device may deactivate an interface configured for communication with the other electronic device. The controller may manage time periods and time period counters to determine when the check whether to reactivate the interface or conclude that the other external device is non-compliant.

Device soft-start management for enumeration problems with USB hosts

Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.

Method and apparatus to tune a toggle mode interface

A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Self-calibrating relaxation oscillator based clock cycle

Self-calibrating relaxation oscillator based clock source

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Bengaluru, India

Srinivasa Rao Sabbineni