Texas Instruments Corporation

Srinivasa Raghavan Sridhara

Raviprakash Suryanarayana Rao

Theodore Warren Houston

Pierre Bertrand

Parvinder Kumar Rana

Vipul Kumar Singhal

Atul Ramakant Lele

Premkumar Seetharaman

Keshav Bhaktavatson Chintamani

Ajith Subramonia

Malav Shrikant Shah

Bharath Kumar Poluri

Sanjeev Kumar Suman

An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array.

Testing retention mode of an SRAM array

An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.

Integrated circuit with low power SRAM

In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

Power gate for latch-up prevention

A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Automatic latch-up prevention in SRAM

An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A diode is electrically connected between a power supply and the positive power supply line connected to the dummy memory cells. The binary logical value is then driven on to the dummy bit line pair. Next, one or more dummy word lines are driven to a logical high allowing selected dummy memory cells to be written with the binary logical value. After the selected dummy memory cells have been written to, the one or more dummy word lines are driven to a logical low. Next the diode is disabled by turning on a PFET connected between the power supply and the positive power supply line. Turning on the PFET also electrically connects the power supply to the positive power supply line.

Initializing dummy bits of an SRAM tracking circuit

An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to drive the dummy bit lines is selected. A binary logical value is written to a memory cell in the SRAM. The single dummy word line and a word line containing the memory cell in the SRAM are driven to logical high values concurrently. A dummy bit line, driven by the dummy memory cells, drives an input of a buffer to a binary logical value stored in the dummy memory cells. An output of the buffer enables a sense amp to amplify a voltage developed across the bit lines electrically connected to the memory cell.

Testing signal development on a bit line in an SRAM

An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects, based on N bits from a row address in a memory array, which tracking circuit from a group of 2tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal. A second multiplexer selects, based on the N bits from the row address for a memory array, which output from the tracking circuits is used to enable the sense amp enable signal.

Channel hot carrier tolerant tracking circuit for signal development on a memory SRAM

A method for controlling a hold buffer delay is provided. A control voltage is generated in response to a measurement of at least one of process variation, temperature variation, and supply voltage variation to compensate for a hold violation, and the delay of a buffer is adjusted using the control voltage. A first data signal is provided in synchronization with a first clock signal. A logic operation is performed on the first signal so as to generate a second data signal. A third data signal is generated and outputted in synchronization with a second clock signal, and at least one of the first and second data signals is buffered with the buffer.

Method and apparatus to compensate for hold violations

User equipment (UE)-initiated accesses within a cellular network include non-synchronized random access requests when the UE is not synchronized with a base station that is serving a cell occupied by the UE. The random access request is formed by generating a set of samples at a selected sample rate, such that the set of samples spans a specified duration period, wherein the sample rate is one of a plurality of different sample rates enabling different implementations of the random access transmission. The specified duration period is integrally divisible by each of the plurality of different sample periods.

Random access cyclic prefix dimensioning in wireless networks

A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be embedded within a large-scale integrated circuit, for example in combination with a microprocessor and associated circuitry. Upon system control circuitry determining that an SRAM array can be operated in a read-only mode, for example that a large number of read operations are likely to be performed prior to writing to the SRAM array, the power supply voltages applied to the SRAM array are reduced. The array power supply voltage and periphery power supply voltage can be at separate voltages and separately reduced from the read/write mode to the read-only mode. The read-only mode can be readily used for instruction cache memories, and for local instruction memories associated with an embedded microcontroller.

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Plano, TX, United States of America

Srinivasa Raghavan Sridhara