Intel Corporation

Everspin Technologies, Inc.

Freescale Semiconductor,inc.

Tahoe Research, Ltd.

Srinivas V Pietambaram

Kristof Darmawikarta

Rahul N Manepalli

Sri Ranga Sai Boyapati

Robert Alan May

Aleksandar Aleksov

Gang Duan

Jon Michael Slaughter

Nicholas David Rizzo

Brandon C Marin

Hiroki Tanaka

Debendra Mallik

Renu Whig

Jeremy D Ecton

Tarek A Ibrahim

Jason A Janesky

Dilan Seneviratne

Bengt J Akerman

Robert L Sankman

Renu Whig Dave

Sameer Paital

Jung Kyu Han

Sashi S Kandanur

Ravindranath Vithal Mahajan

Javier Soto Gonzalez

Suddhasattwa Nad

Steve S Cho

Bharat P Penmecha

Benjamin Duong

Jijun Sun

Yonggang Li

Xiaoying Guo

Thomas Heaton

Shawna M Liff

Kyu Oh Lee

Junnan Zhao

Prithwish Chatterjee

Bai Nie

Telesphor Kamgaing

Omkar G Karhade

Yikang Deng

Chong Zhang

Deepak Kulkarni

Xiaoqian Li

Frank Truong

Darko Grujicic

Kemal Aygun

Nitin A Deshpande

Phillip G Mather

Cheng Xu

Leonel R Arana

Ji Yong Park

Ying Wang

Changhua Liu

Matthew L Tingey

Rui Zhang

Chung Kwang Christopher Tan

Rahul Jain

Mitul Bharat Modi

Sai Vadlamani

Sheng C Li

Andrew James Brown

Xavier Francois Brun

Praneeth Kumar Akkinepally

Nadine L Dabby

Jason M Gamba

Yosuke Kanaoka

Hongxia Feng

Marcel Arlan Wall

Jesse Jones

Adel A Elsherbini

Sujit Sharan

Mauro J Kobrinsky

James E Jaussi

Zhiguo Qian

Zhichao Zhang

Islam A Salama

Pooya Tadayon

Joshua Heppner

Vivek Raghunathan

Thomas L Sounart

Andrew Paul Collins

Dingying David Xu

Gregory W Grynkewich

Kenneth H Smith

Sri Chaitra Jyotsna Chavali

Brian R Butcher

Braxton L Lathrop

Amanda E Schuckman

Siddharth K Alur

Mark S Hlad

Kyu-Oh Lee

Lauren Ashley Link

Kousik Ganesan

Meizi Jiao

Arnab Sarkar

Oscar Ojeda

Whitney Michael Bryks

Jiwei Sun

Tatyana N Andryushchenko

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

Embodiments disclosed herein include disaggregated die modules. In an embodiment, a disaggregated die module comprises a plurality of core logic blocks. In an embodiment, the disaggregated die module further comprises a first IO interface, where the first IO interface is adjacent to an edge of the disaggregated die module, and a second IO interface, where the second IO interface is set away from the edge of the disaggregated die module.

Flexible die to floor planning with bump pitch scale through glass core via pitch

Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

Photonic interconnect and components in glass

Embodiments herein relate to systems, apparatuses, or processes directed to an integrated optical coupler that may be used to optically couple a waveguide and a PIC. In embodiments, the integrated optical coupler may include an optical diffraction grating mechanism, an optical lens, and a Faraday rotator. In embodiments, the integrated optical coupler may at least partially within a housing. Other embodiments may be described and/or claimed.

Integrated optical coupler

Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

Faraday rotator interconnect as a through-via configuration in a patch architecture

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.

Position controlled waveguides and methods of manufacturing the same

Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

Hybrid bonding technologies with thermal expansion compensation structures

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

Methods and apparatus to increase glass core thickness are disclosed. An example apparatus includes a first glass substrate, a second glass substrate, an interface layer between the first glass substrate and the second glass substrate, the interface layer coupling the first glass substrate to the second glass substrate, and an interconnect extending through at least a portion of the first glass substrate and at least a portion of the second glass substrate.

Methods and apparatus to increase glass core thickness

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Photonic integrated circuit packaging architectures

The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.

Carrier chuck comprising a plurality of magnets and methods of forming and using thereof

The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

Optimization for raster scanning

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Growing community of inventors

Gilbert, AZ, United States of America

Srinivas V Pietambaram