Intel Corporation

Everspin Technologies, Inc.

Freescale Semiconductor,inc.

Tahoe Research, Ltd.

Srinivas V Pietambaram

Kristof Darmawikarta

Rahul N Manepalli

Sri Ranga Sai Boyapati

Robert Alan May

Jon Michael Slaughter

Gang Duan

Aleksandar Aleksov

Nicholas David Rizzo

Renu Whig

Brandon C Marin

Hiroki Tanaka

Debendra Mallik

Jason A Janesky

Dilan Seneviratne

Bengt J Akerman

Robert L Sankman

Tarek A Ibrahim

Renu Whig Dave

Jung Kyu Han

Ravindranath Vithal Mahajan

Javier Soto Gonzalez

Steve S Cho

Sameer Paital

Sashi S Kandanur

Ali Lehaf

Jijun Sun

Yonggang Li

Jeremy D Ecton

Suddhasattwa Nad

Xiaoying Guo

Bharat P Penmecha

Thomas Heaton

Shawna M Liff

Kyu Oh Lee

Junnan Zhao

Prithwish Chatterjee

Yikang Deng

Chong Zhang

Deepak Kulkarni

Frank Truong

Benjamin Duong

Telesphor Kamgaing

Kemal Aygun

Phillip G Mather

Cheng Xu

Ji Yong Park

Ying Wang

Matthew L Tingey

Rui Zhang

Chung Kwang Christopher Tan

Darko Grujicic

Omkar G Karhade

Rahul Jain

Leonel R Arana

Sheng C Li

Andrew James Brown

Praneeth Kumar Akkinepally

Changhua Liu

Nadine L Dabby

Yosuke Kanaoka

Bai Nie

Hongxia Feng

Marcel Arlan Wall

Jesse Jones

Jieying Kong

Cemil S Geyik

Adel A Elsherbini

Mauro J Kobrinsky

Nitin A Deshpande

Zhiguo Qian

Islam A Salama

Pooya Tadayon

Joshua Heppner

Vivek Raghunathan

Mitul Bharat Modi

Sai Vadlamani

Thomas L Sounart

Gregory W Grynkewich

Kenneth H Smith

Dingying David Xu

Sri Chaitra Jyotsna Chavali

Braxton L Lathrop

Brian R Butcher

Amanda E Schuckman

Siddharth K Alur

Mark S Hlad

Kyu-Oh Lee

Lauren Ashley Link

Xiaoqian Li

Kousik Ganesan

Meizi Jiao

Jason M Gamba

Oscar Ojeda

Tatyana N Andryushchenko

Jiwei Sun

Whitney Michael Bryks

Shivasubramanian Balasubramanian

Haobo Chen

Haifa Hariri

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

Methods and apparatus to increase glass core thickness are disclosed. An example apparatus includes a first glass substrate, a second glass substrate, an interface layer between the first glass substrate and the second glass substrate, the interface layer coupling the first glass substrate to the second glass substrate, and an interconnect extending through at least a portion of the first glass substrate and at least a portion of the second glass substrate.

Methods and apparatus to increase glass core thickness

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

Photonic integrated circuit packaging architectures

The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.

Carrier chuck comprising a plurality of magnets and methods of forming and using thereof

The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

Optimization for raster scanning

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a through glass via (TGV). The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

Glass substrates having signal shielding for use with semiconductor packages and related methods

An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

In-plane inductors in IC packages

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.

Microelectronic structures including glass cores

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Chiplet first architecture for die tiling applications

A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

Inorganic-based embedded-die layers for modular semiconductive devices

An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

Coreless electronic substrates having embedded inductors

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Heterogeneous nested interposer package for IC chips

An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein

Growing community of inventors

Gilbert, AZ, United States of America

Srinivas V Pietambaram