Qualcomm Incorporated

Srinivas Turaga

Bharat Kumar Rangarajan

Keith Alan Bowman

Dipti Ranjan Pal

Shih-Hsin Jason Hu

Vijayakumar Ashok Dibbad

Rajesh Arimilli

Prashant Dinkar Karandikar

Venkata Biswanath Devarasetty

Harshit Tiwari

Prashanth Kumar Kakkireni

Nagashree Ganapati Upadhya

Deva Sudhir Kumar Pulivendula

Chandan Agarwalla

Pradeep Venkatasubbarao

Vivekanandan Naveen

Shubham Sangal

Shreya Pandurang Math

Akshay Kumar Gupta

Ateesh Deepankar De

Manmohan Manoharan

In a computing device having a pipeline of image processing components, DCVS bandwidth voting may be based on a feedforward compression ratio determined by the first image processing component in the pipeline. The DCVS bandwidth voting may be based on the result of a comparison of change in the feedforward compression ratio with a threshold. Transaction initiator components in the pipeline may select their votes for bandwidth from among a feedforward compression ratio-based value and one or more other values, based on the result of the comparison with the threshold. DCVS parameters may be selected based on bandwidth votes received from transaction initiator components.

Dynamic clock and voltage scaling (DCVS) lookahead bandwidth voting using feedforward compression ratio

A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.

On-die voltage-frequency security monitor

Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

Core voltage regulator energy-aware task scheduling

In certain aspects, a tag memory comprises a plurality of non-configurable tag columns configured to be powered on during a normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during the normal operation and a second portion of the plurality of configurable tag columns is configured to be powered on during the normal operation.

System physical address size aware cache memory

Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Method and system for improving rock bottom sleep current of processor memories

A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.

Power-aware CPU power grid design

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Bengaluru, India

Srinivas Turaga