Cadence Design Systems, Inc.

Srinivas R Kommoori

Bharat Bhushan

Harsh Dev Sharma

Rajeev Srivastava

Mithunjoy Parui

Albert Lee

Po-chiang Albert Lee

Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.

Visual yield analysis of intergrated circuit layouts

According to various embodiments of the invention electronic circuit design information can be presented to a designer by determining an electronic circuit comprising at least two gates and by determining a distance of one gate relative to another gate in a stage. A visual indicator for the stage can be calculated based on the distances between at least two gates in the stage. The visual indicator can then be displayed. The visual indicator can be a color and the relative distance can be indicated by brightness, hue or saturation, etc. Alternatively, the visual indicator can be a pattern and the relative distance between at least two gates can be indicated by darkness of the pattern.

Graphical user interface for prototyping early instance density

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Milpitas, CA, United States of America

Srinivas R Kommoori