Texas Instruments Corporation

Srinivas Kumar Vooka

Rahul Gulati

Rubin Ajit Parekhji

Arvind Jain

Sundarrajan Subramanian

Pranav Murthy

Prashant Mohan Kulkarni

Vishwanath S

Ratheesh Thekke Veetil

On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input.

On-chip field testing methods and apparatus

A scannable integrated circuit () including a functional integrated circuit (P, P) having scan chains, multiple scan decompressors (), each operable to supply scan bits to some of the scan chains (), a shared scan-programmable control circuit (), a tree circuit () coupled with the functional integrated circuit (P, P), the shared scan-programmable control circuit () coupled to control the tree circuit (), and a selective coupling circuit () operable to provide selective coupling with the shared scan-programmable control circuit () for scan programming through any of the multiple scan decompressors (). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.

Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making

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Kaggadasapura, India

Srinivas Kumar Vooka