Texas Instruments Corporation

Standard Microsystems Corporation

Smsc Holdings Sarl

Srinivas Kumar Pulijala

Vadim Valerievich Ivanov

Steven Graham Brantley

Bharath Karthik Vasan

Jerry Doorenbos

Paul F Illegems

Munaf Hussain Shaik

Piyush Kaslikar

Siva Kumar Sudani

Scott Cameron McLeod

Martijn Fridus Snoeij

Vivek Varier

Patrick Forster

Miroslav Oljaca

YuGuo Wang

An example apparatus includes: a folded cascode circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first feedback loop including a third output terminal, the third output terminal coupled to the first output terminal; a second feedback loop including a fourth output terminal, the fourth output terminal coupled to the second output terminal; and a first driver including a first control terminal and a fifth output terminal, the first control terminal coupled to the third output terminal; and a second driver including a second control terminal and a sixth output terminal, the second control terminal coupled to the fourth output terminal, the sixth output terminal coupled to the fifth output terminal.

Amplifier output stage circuitry

In an example, a circuit includes a first field-effect transistor (FET) having a gate and first and second terminals. The circuit includes a second FET having a gate and first and second terminals, the second terminals of the first and second FETs coupled together. The circuit includes a first boosted follower coupled to the gate of the first FET and includes a second boosted follower coupled to the gate of the second FET. A third FET is coupled to the first boosted follower and the second voltage terminal and configured to turn off the first boosted follower responsive to a first level of an output voltage. A fourth FET is coupled to the second boosted follower and the first voltage terminal and configured to turn off the second boosted follower responsive to a second level of the output voltage.

Voltage buffer

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

Class AB monticelli output stage design with bias temperature instability tolerance

A device comprises a voltage limiter, two capacitors, a resistor, and a voltage follower buffer. The voltage limiter has a first input coupled to a reference voltage rail, a second input coupled to a supply voltage rail, and two voltage limiter outputs. The first capacitor is coupled between a device output and the first voltage limiter output, and the resistor is coupled between the first and second voltage limiter outputs. The voltage follower buffer has an input coupled to the first voltage limiter output and a voltage follower buffer output. The second capacitor is coupled between a device input and the voltage follower buffer output. In some implementations, a resistance of the resistor is greater than a capacitance of the first capacitor. In some implementations, a third capacitor is coupled between the device input and the device output.

Nonlinear frequency compensation system

In an example, a device includes a semiconductor substrate having a top surface. The device also includes a P-doped well formed in the semiconductor substrate and extending downwardly from the top surface. The device includes a cathode of a diode formed by an N-doped region in the P-doped well. The device also includes an anode of the diode formed by a P-doped region, the P-doped region spaced away from the N-doped region in the P-doped well. The device includes a deep N-type buried layer (DNBL) formed in the semiconductor substrate, the P-doped well formed between the top surface and the DNBL. The device also includes an N-doped well extending from the top surface to the DNBL.

Ultra-low leakage diodes used for low input bias current

An example apparatus includes: An amplifier comprising folded cascode circuitry having an input and an output, an input pair coupled to the input, clamp circuitry including: a first transistor having a first drain, a first source, and a first gate, the first source coupled to the output, a second transistor having a second drain, a second source, and a second gate, the second drain coupled to the first drain and the second gate coupled to the first drain and second drain, a third transistor having a third drain, a third source, and a third gate, the third source coupled to the output, and a fourth transistor having a fourth drain, a fourth source, and a fourth gate, the fourth drain coupled to the third drain and the fourth gate coupled to the third drain and the fourth drain.

Methods and apparatus to improve performance of amplifiers

Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.

Trimming operational amplifiers

A current measurement and control circuit may comprise a shunt resistor coupled between supply and output nodes; a first resistor coupled to the supply node; a second resistor coupled to ground; and a transconductance amplifier having an input coupled to the first resistor to define a compensation node and another input coupled to the output node. The circuit may also include a first transistor having a first current terminal coupled to the compensation node and a second current terminal coupled to the second resistor to define a measurement node; and a second transistor having a first current terminal coupled to ground and a second current terminal coupled to the output node. The circuit may also include an ADC having an analog input coupled to the measurement node; an IDAC having an analog output coupled to the compensation node; and switches to set the circuit in a measurement or a compensation mode.

Current measurement and control system

In examples of a chopper operational amplifier, a current control circuit comprises a pair of voltage sources, each of which may be varied to generate a voltage signal of a particular value, and multiple inverters, each of which is configured to receive either a clock signal or its complement signal and one of the voltage signals. Based on these inputs, each inverter generates a control signal that is delivered to a corresponding switch in the input stage of the chopper operational amplifier to control the gate voltage of that switch. Based on the difference between the values of the voltage signals, the current control circuit operates to reduce the amplitudes of base currents induced by charge injection at the input terminals of the chopper operational amplifier.

Input current trim for chopper operational amplifier

A circuit includes an operational amplifier having: a positive input; a negative input; an operational amplifier output; a differential front end; a positive channel (PCH) input stage; a negative channel (NCH) input stage; and an output stage. The operational amplifier also includes a current limit circuit coupled to an output of the output stage and including: an output current sense voltage circuit having an output configured to provide an output current sense voltage; an indirect current feedback circuit coupled to the output of the output current sense voltage circuit, the indirect current feedback circuit having an output configured to provide an output current feedback sense voltage responsive to the output current sense voltage; and control circuitry coupled to the indirect current feedback circuit and configured vary a resistance between the output stage output and ground responsive to a difference between the output current feedback sense voltage and a reference voltage.

Operational amplifier with indirect current feedback current limiter

Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.

Differential input circuits with input voltage protection

An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

Operational amplifier offset trim

An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.

Operational amplifier input stage with high common mode voltage rejection

A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

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Tucson, AZ, United States of America

Srinivas Kumar Pulijala