Applied Materials, Inc.

Srinivas Guggilla

Deenesh Padhi

Xianmin Tang

Yong Cao

Yana Cheng

Mehul B Naik

Paul F Ma

Karthik Janakiraman

Rui Cheng

He Ren

Zubin Huang

Diwakar N Kedlaya

Meenakshi Gupta

Er-Xuan Ping

David P Thompson

Wei W Wang

Anantha K Subramani

Xinhai Han

Ashish Goel

Kevin Vincent Moraes

Gene S Lee

Yung-chen Lin

Hanbing Wu

Weifeng Ye

Hidetaka Oshio

Sree Rangasai V Kesapragada

Chao Li

Tzu-shun Yang

Lavinia Nistor

Mei Yin Chang

Rongjun Wang

Alexandros T Demos

Gongda Yao

Bhaskar Kumar

Weimin Zeng

Tae Hong Ha

Daniel Lee Diehl

Thanh X Nguyen

Gilbert Hausmann

Nitin Khurana

Suraj Rengarajan

Priyanka Dash

Sree Rangasai Kesapragada

Martin Kranz

Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Multi-layer stacks for 3D NAND extendability

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Multiple spacer patterning schemes

Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.

Methods for modifying photoresist profiles and tuning critical dimensions

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.

Methods and apparatus for co-sputtering multiple targets

In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Methods for depositing dielectric barrier layers and aluminum containing etch stop layers

Multi-layer stacks for 3D NAND extendibility

A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.

Method and apparatus for protecting metal interconnect from halogen based precursors

Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

Interconnect structures and methods of formation

A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.

Aluminum nitride barrier layer

In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

Methods for depositing dielectric films via physical vapor deposition processes

Generally, a method for pre-cleaning native oxides and other contaminants from apertures on a substrate is provided. In one embodiment, a method for pre-cleaning apertures on a substrate includes disposing the substrate on a support member in a process chamber, cooling the substrate at least to a temperature of 100 degrees Celsius, and exposing the substrate to a pre-clean process. In another embodiment, a method for pre-cleaning apertures on a substrate includes cooling the substrate at least to a temperature of 100 degrees Celsius in a first chamber, transferring the substrate to a second chamber and pre-cleaning the substrate in the second chamber while maintaining a substrate temperature of 100 degrees Celsius.

Method and apparatus for cleaning substrates

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San Jose, CA, United States of America

Srinivas Guggilla