Applied Materials, Inc.

Appled Materials, Inc.

Srinivas Gandikota

Abhijit Basu Mallick

Yixiong Yang

Jacqueline S Wrench

Susmit Singha Roy

Seshadri Ganguli

Yihong Chen

Xinyu Fu

Yu Lei

Steven C H Hung

Kelvin Chan

Wei V Tang

Pramit Manna

Avgerinos V Gelatos

Shih Chung Chen

Mei Yin Chang

Muhammad M Rasheed

Xinliang Lu

Mandyam Sriram

Ziqing Duan

Rui Cheng

David P Thompson

Xianmin Tang

Deenesh Padhi

Girish Anant Dixit

Bo Zheng

Eswaranand Venkatasubramanian

Jeffrey W Anthis

Sang Ho Yu

Rongjun Wang

Tza-Jing Gung

Srinivas D Nemani

Wei D Wang

Steve G Ghanayem

Joung Joo Lee

Annamalai Lakshmanan

Benjamin Schmiege

Mario Dan Sanchez

Ludovic Godet

Hoon Sik Kim

Karthik Janakiraman

Dien-Yeh Wu

Maitreyee Mahajani

Naomi Yoshida

Sanjay S Natarajan

Jianxin Lei

Wen Xiao Chen

Michael Xiaoxuan Yang

Wei Liu

Hua Chung

Joseph Yudovsky

Robin W Cheung

Robert Jan Visser

Anantha K Subramani

Paul F Ma

Praburam Gopalraja

Ming Xi

Gaurav Thareja

Yong Cao

Jeong Soo Byun

Ananthkrishna Jupudi

Mukund Srinivasan

Kevin Griffin

Prerna Sonthalia Goradia

Patricia M Liu

Jared Ahmad Lee

Regina Germanie Freed

Muhannad Mustafa

Swaminathan T Srinivasan

Ken Kaung Lai

Uday Mitra

Nikolaos Bekiaris

Kartik Ramaswamy

Yang Yang

Mehul B Naik

Liang-Yuh Chen

Siddarth A Krishnan

Keith A Miller

Kirankumar Neelasandra Savandaiah

He Ren

Michael Santiago Cox

Lara Hawrylchak

Fusen E Chen

Lan Yu

Chien-Teh Kao

Mohith E Verghese

Benjamin Colombeau

Suketu Arun Parikh

Zhebo Chen

Adolph Miller Allen

Seshadri Ramaswami

Timothy Joseph Franklin

Wei Ti Lee

Kurtis Leschkies

Xiaoxiong Yuan

Yu Wen Chang

Liang Light Chen

Zhenbin Ge

Takehito Koshizawa

Sang-Hyeob Lee

Methods for depositing a metal contact stack on a substrate are described. The metal stack includes a metal cap layer and a molybdenum conductor layer. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity metal contact stack

A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, wherein the barrier layer is TiN; and forming a metal layer in the feature and over the barrier layer, wherein the metal layer is at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).

Methods and apparatus for seam reduction or elimination

Methods for filling a substrate feature with a seamless metal gate fill are described. Methods comprise sequentially depositing a film on a substrate surface having at least one feature thereon. The at least one feature extends a feature depth from the substrate surface to a bottom surface and has a width defined by a first sidewall and a second sidewall. The film is treated with an oxidizing plasma. Then the film is etched to remove the oxidized film. A second film is deposited to fill the feature, where the second film substantially free of seams and voids.

Seamless gapfill of metal nitrides

Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.

Nucleation-free gap fill ALD process

Methods for depositing film comprising cyclical exposure of a substrate surface to a precursor and a degas environment to remove gas evolved from the film. Some embodiments further comprise the incorporation poisoning the top of a feature to inhibit film growth at the top of the feature. Some embodiments further comprising etching a portion of the film deposited at the top of a feature between cycles to increase gap-fill uniformity.

Deposition of conformal and gap-fill amorphous silicon thin-films

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

Liner for V-NAND word line stack

A processing method comprises positioning a substrate in a processing chamber and setting a temperature of the substrate to a range of 50° C. to 500° C.; conducting an atomic layer deposition (ALD) cycle on the substrate; and repeating the ALD cycle to form a silicon oxide film. The ALD cycle comprises: exposing the substrate to an aminosilane precursor in the processing chamber by pulsing a flow of the aminosilane precursor; purging the processing chamber of the aminosilane precursor; exposing the substrate to an oxidizing agent by pulsing a flow of the oxidizing agent for a duration in a range of greater than or equal to 100 milliseconds to less than or equal to 3 seconds; and purging the processing chamber of the oxidizing agent.

Deposition of silicon-based dielectric films

Methods of forming electronic devices comprising tungsten film stacks are provided. Methods include forming a tungsten nucleation layer on the barrier layer using an atomic layer deposition (ALD) process including a tungsten precursor that is free of fluorine. Forming the nucleation layer comprises controlling process parameters and/or forming WSi pre-nucleation layer.

Method of reducing titanium nitride etching during tungsten film formation

A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.

Metal based hydrogen barrier

A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region.

MOSFET gate engineerinng with dipole films

A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

Threshold voltage modulation for gate-all-around FET architecture

Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

Enhancing gapfill performance of dram word line

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

Integrated dipole region for transistor

Methods and apparatus for processing a substrate is provided herein. For example, a method for processing a substrate comprises depositing a silicide layer within a feature defined in a layer on a substrate, forming one of a metal liner layer or a metal seed layer atop the silicide layer within the feature via depositing at least one of molybdenum (Mo) or tungsten (W) using physical vapor deposition, and depositing Mo using at least one of chemical vapor deposition or atomic layer deposition atop the at least one of the metal liner layer or the metal seed layer, without vacuum break.

Methods and apparatus for processing a substrate

A sacrificial sealing layer is formed on a high-κ metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-κ metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-κ metal oxide layer to form a dipole region.

Amorphous silicon-based scavenging and sealing EOT

Growing community of inventors

Santa Clara, CA, United States of America

Srinivas Gandikota