Xilinx, Inc.

Srinivas Beeravolu

Nabeel Shirazi

Vinod Kumar Kathail

Adam P Donlin

Shail Aditya Gupta

Shay Ping Seng

Khang Kim Dao

Jeffrey H Seltzer

Amit Kasat

Kyle Corbett

Pradip Jha

Jeffrey Mark Arnold

Suman Kumar Timmireddy

Dinesh K Monga

Vishal Suthar

Chukwuweta Chukwudebe

Vidhumouli Hunsigida

Jaipal R Nareddy

Christopher J Case

Stephen L Bade

Anindita Patra

Adithya Balaji Boda

Biping Wu

Kalyani Tummala

Ayush Khemka

Siddarth Rele

Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.

Block design containers for circuit design

Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.

Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip

For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Hardware-software design flow for heterogeneous and programmable devices

Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.

System level circuit design

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Los Gatos, CA, United States of America

Srinivas Beeravolu