International Business Machines Corporation

Srinivas Bangalore Purushotham

Charles Francis Marino

Srinivasan Ramani

Madhavan Srinivasan

Sooraj R Nair

Alper Buyuktosunoglu

Diyanesh B Chinnakkonda Vidyapoornachary

Prasanna Jayaraman

Tobias Webel

Preetham M Lobo

Ramon Bertran Monfort

Pradeep Bhadravati Parashurama

Martin Recktenwald

David John Krolak

Venkata K Tavva

Santosh Balasubramanian

Deepak K Gangadhar

Naveen Miriyalu

A method, computer program product, and/or system is disclosed for changing the events monitored by a processor including: determining whether a change in the monitoring of the first event to the second different event has been requested; copying, in response to a request to change the monitoring of the first event to the second different event, op-codes from memory into microcode executable by a general processing engine; and executing the op-codes from memory by the general processing engine to change the first event monitored by the counter to the second different event.

Methods and systems for dynamic reconfiguring of hardware performance monitoring unit (PMU) events

Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.

Voltage overshoot management

Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.

Voltage droop management through microarchitectural stall events

A method for managing memory within a computing system. The method includes one or more computer processors identifying a range of physical memory addresses that store a first data. The method further includes determining whether a second data is stored within the range of physical memory addresses that stores the first data. The method further includes responding to determining that the second data is stored within the range of physical memory addresses that store the first data, by determining whether a process accessing the second data is identified as associated with a side-channel attack. The method further includes responding to determining that the process accessing the second data is associated with the side-channel attack, by initiating a response associated with the process accessing the second data.

Identifying and responding to a side-channel security threat

A method handles cache misses using a Scope Resolution Tag Buffer (SRTB). A cache controller assigns each data block in L2 cache with an n-bit value, where the n-bit value describes a quantity of occurrences in which the data block has been accessed, and where the cache controller increments the n-bit value in one or more data blocks in the first level memory cache each time the one or more data blocks are accessed. The cache controller evicts a particular data block from the L2 cache, and stores a particular data block address where the particular data block is now stored in a Scope Resolution Tag Buffer (SRTB). The information in the SRTB is used to locate which cache or memory contains the particular data block in the event of a subsequent cache miss in the L2 cache.

Scope resolution tag buffer to reduce cache miss latency

Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.

Method for performance monitoring using a redundancy tracking register

A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.

Memory activity driven adaptive performance measurement

A method for monitoring performance of events occurring in a multiprocessor system is provided where the performance monitoring units (PMUs) are globally synchronized. The global synchronization is carried out with a dedicated bit field set to any of pause, stop, restart, or reset command. The command is sent across the scan communications interface (SCOM) of all chips by using existing fabric connecting all nest units to control the PMUs in the system. A pre-scale counter before a main counter may be used to buffer event counts until a reset or a restart command is sent to the SCOM in the system.

Processor performance monitoring unit synchronization

A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.

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Bengaluru, India

Srinivas Bangalore Purushotham