Advanced Micro Devices Corporation

Globalfoundries Inc.

Srinath Krishnan

Witold P Maszara

William George En

Dong-Hyuk Ju

Zoran Krivokapic

Matthew S Buynoski

Bin Yu

Ming-Ren Lin

Judy Xilin An

Geoffrey Choh-Fei Yeap

Qi Xiang

Effiong Etukudo Ibok

Shekhar Pramanick

Emi Ishida

Stephen G Beebe

Ming Yin Hao

Jerry G Fossum

Xilin Judy An

Meng-Hsueh Chiang

James N Pan

John Christian Holst

Jung-Suk Goo

Mario M Pelella

Richard K Klein

Concetta E Riccobene

Ming-Yin Hao

David S Bang

Jia Feng

Zhi-Yuan Wu

Ihsan Djomehri

Juhi Bansal

Siu Lun Lee

Mario P Pelella

Zoran Krivakapic

A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Modeling gate transconductance in a sub-circuit transistor model

A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Shallow trench isolation process utilizing differential liners

The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

Dual SOI film thickness for body resistance control

A structure, for testing relative to an MOS transistor, closely resembles the MOS transistor of interest. For example, certain dimensions and a number of dopant concentrations typically are substantially the same in the test structure as found in corresponding elements of the MOS transistor of interest. However, the regions of the test structure corresponding to the source and drain of the transistor have no halos or extensions that might cause gate overlap; and in the test structure, these regions are of a semiconductor type opposite the type found in the source and drain of the transistor. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for direct electrical measurement of gate length.

Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies

A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.

SOI device with structure for enhancing carrier recombination and method of fabricating same

A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of the transistor. Gate insulator and polysilicon layers are formed, and the polysilicon is implanted with dopant, to a concentration level expected in the transistor gate. After gate patterning, the methodology involves forming sidewall spacers and implanting dopant into the active device well, to form regions in the test structure corresponding to the transistor source and drain. Although the concentrations mimic those in the transistor source and drain, these test structure regions are doped with opposite type dopant material. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for measurement of gate length.

Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS

A method of manufacturing a semiconductor device includes forming a gate, source/drain extensions, buffer regions, and source/drain regions. The gate is formed over a semiconductor layer, and the source/drain extensions are formed within the semiconductor layer and adjacent the gate. The buffer regions are formed within first amorphous implant regions, and the source/drain regions are formed within second amorphous implant regions. The buffer regions and the source/drain regions are activated using solid-phase epitaxy whereby sidewalls of the activated buffer regions and the activated source/drain regions are substantially vertical.

Tip architecture with SPE for buffer and deep source/drain regions

A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.

Method of growing as a channel region to reduce source/drain junction capacitance

An SOI semiconductor and method for making the same includes a substrate and dielectric support structures that support a silicon body above the substrate. This creates a void underneath the silicon body and thereby reduces the capacitance between the source/drain regions on body and the substrate.

Semiconductor device with a silicon-on-void structure and method of making the same

A method of making a Silicon-on-Insulator (SOI) transistor includes forming a body layer that is fully depleted when the SOI transistor is in a conductive state and forming first p regions adjacent each of the SOI transistor source/drain regions to adjust the SOI transistor threshold voltage. To suppress punch-through current, an additional implant step is carried out to form second p regions adjacent first implant regions.

Method of making a hybrid SOI device that suppresses floating body effects

A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure

An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

SOI MOSFET having amorphized source drain and method of fabrication

An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.

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Campbell, CA, United States of America

Srinath Krishnan