Marvell Asia Pte., Ltd.

Cavium, Inc.

Srinath Atluri

Weihuang Wang

Gerald Schmidt

Weinan Ma

Shrikant Sundaram Lnu

Premshanth Theivendran

Tsahi Daniel

Sowmya Hotha

Jeffrey T Huynh

Mohan Balan

Nikhil Jayakumar

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Hierarchical statisically multiplexed counters and a method thereof

Embodiments of the present invention are directed to a wildcard matching solution that uses a combination of static random access memories (SRAMs) and ternary content addressable memories (TCAMs) in a hybrid solution. In particular, the wildcard matching solution uses a plurality of SRAM pools for lookup and a spillover TCAM pool for unresolved hash conflicts.

Hybrid wildcard match table

A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.

Barrel compactor system, method and device

Hierarchical statistically multiplexed counters and a method thereof

Systems and methods for inserting flops at the chip-level to produce a signal delay for preventing buffer overflow are disclosed herein. Shells of modules described in an RTL description and their connections are analyzed to determine a signal latency between a sender block and a receiver block. The logical interfaces of the shells are grouped in a structured document with associated rules. Flops are inserted between the sender block and the receiver block to introduce a flop delay to meet physical design timing requirement and prevent a buffer of the receiver block from overflowing due to data that is already in-flight when a flow control signal is sent by the receiver block. The sum of a delay on a data line and a delay on a flow control line measured in clock cycles must be less than a depth of the buffer.

Approach for chip-level flop insertion and verification based on logic interface definition

A policer system on one or more place and/or route blocks. The policer system including a plurality of local physical policers each stored in a plurality of physical memory banks and coupled with a plurality of global policers stored in one or more global banks separate from the physical banks. Thus, each bank of the global policers are able to represent a logical combination of a plurality of the physical banks of physical policers.

Policer architecture

A network switch comprises a plurality of packet processing units configured to process a received packet through multiple packet processing stages based on search result of a table. The network switch further comprises one or more memory units configured to maintain the table to be searched and provide the search result to the packet processing units. The network switch further comprises a table managing unit configured to accept a plurality of rules on bulk update to the table specified by a control unit, and perform the bulk update on the table based on the rules specified by the control unit without the control unit accessing the table directly for the bulk update.

Apparatus and method for fast search table update in a network switch

A network switch comprises a packet processing pipeline including a plurality of packet processing clusters configured to process a received packet through multiple packet processing stages based on table search/lookup results. The network switch further includes a plurality of search logic units each corresponding one of the plurality of packet processing clusters, wherein each of the search logic units is configured to convert a unified search request of a table from its corresponding packet processing cluster to a plurality table search commands specific to one or more memory clusters that maintain the table, provide the plurality table search commands specific to the memory clusters in parallel and collect and provide the table search results from the memory clusters to the corresponding packet processing cluster. The network switch further includes said one or more memory clusters configured to maintain the table to be searched, search the table in parallel according to the plurality table search commands from the search logic unit, and process and provide the table search results to the search logic unit.

Growing community of inventors

Fremont, CA, United States of America

Srinath Atluri