Texas Instruments Corporation

Srinadh Madhavapeddi

Nikolaus Klemmer

Jaimin A Mehta

Hamid Safiri

Baher S Haroun

Srinivas Lingam

Charles Kasimer Sestok, Iv

Krishnasawamy Nagaraj

Terry Lee Sculley

Timothy F Murphy

Joonsung Park

Hunsoo Choo

Neeraj P Nayak

Roy David Wojciechowski

Pradip Thaker

Vijayavardhan Baireddy

Scott Adam Morrison

Mitsuru Shimada

Christopher Barr

Atul Kumar Jain

Navin S Chander

Chan Fernando

A system includes a battery and a monitoring circuit coupled to the battery. The monitoring circuit includes a sense circuit and a peripheral device coupled to the sense circuit. The peripheral device includes a universal asynchronous receiver-transmitter (UART) receiver having an adaptive sample timing circuit with a numerically-controlled oscillator (NCO) circuit. The peripheral device also includes memory coupled to the UART receiver and configured to store battery monitoring data.

UART receiver with adaptive sample timing control using a numerically-controlled oscillator

Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N(k)) based on the second domain clock.

Skew compensation for multi-domain clock generation

Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).

Aperiodic clock generation with spur suppression

A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

On-chip spectral analysis using enhanced recursive discrete Fourier transforms

Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs.

Low phase noise frequency synthesizer

A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.

Scalable distributed routing scheme for PCI express switches

A sequence of data samples and a sequence of non-data samples are provided. Four input samples from one of the data samples and the non-data samples are selected based on a clock signal. At least a portion of contents of a first group of memory cells are stored in a second group of memory cells. The first group of memory cells are comprised of four memory cells. The selected four input samples are stored in the first group of memory cells.

Implementation for a 5 sample guard interval for multi-band OFDM

Growing community of inventors

Dallas, TX, United States of America

Srinadh Madhavapeddi