Advanced Micro Devices Corporation

Microsoft Technology Licensing, LLC

Marvell Asia Pte., Ltd.

Cavium, Inc.

Intel Corporation

Srilatha Manne

Yasuko Eckert

Manish Arora

Shubhendu Sekhar Mukherjee

James Michael O'Connor

Michael J Schulte

Nuwan S Jayasena

Gabriel H Loh

Krysta Marie Svore

Mithuna Shamabhat Thottethodi

Douglas M Carmean

Nicolas Guillaume Delfosse

William Lloyd Bircher

Helmut Gottfried Katzgraber

Christopher Anand Pattison

Lena E Olson

Poulami Das

Indrani Paul

David Asher

Edward J McLellan

Madhu Saravana Sibi Govindan

Syed Ali Jafri

Richard Eugene Kessler

John Kalamatianos

David Albert Carlson

Vilas K Sridharan

Mark Donald Hill

Paul S Keltcher

Shay Gal-On

Sanjay Pant

Alexander Rucker

Youngtaek Kim

Wei T Huang

Mauricio Breternitz, Jr

Isam Wadih Akkawi

Bryan Chin

Xiaodong Wang

Donald W McCauley

Wayne Burleson

Paul B Racunas

Mark Buckler

Kypros Constantinides

Richard E Klass

Rajagopalan Desikan

Can Hankendi

Vignesh Trichy Ravi

Lloyd Bircher

Mahdu S S Govindan

Nitya Ranganathan

Indrain Paul

Syed Ali R Jafri

A system includes a core complex with multiple processor cores and multiple caches. The system also includes system directories that track cache residency in the caches of the core complex. Based at least in part on a power state transition of the core complex a system directory can adjust its capacity to track the cache residency.

Modifying system directory capacity based on power state transition

A device for disabling faulty cores using proxy virtual machines includes a processor, a faulty core, and a physical memory. The processor is responsible for executing a hypervisor that is configured to assign a proxy virtual machine to the faulty core. The assigned proxy virtual machine also includes a minimal workload. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for disabling faulty cores using proxy virtual machines

A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.

Processor data cache with shared mid-level cache and low-level cache

A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Geometry-based compression for quantum computing devices

A quantum computing device comprises at least one quantum register including l logical qubits, where l is a positive integer. The quantum computing device further includes a set of d decoder blocks coupled to the at least one quantum register, where d<2*l. In this way, the decoder blocks may share decoding requests generated by the logical qubits.

Systems for coupling decoders to quantum registers

The size of a cache is modestly increased so that a short pointer to a predicted next memory address in the same cache is added to each cache line in the cache. In response to a cache hit, the predicted next memory address identified by the short pointer in the cache line of the hit along with an associated entry are pushed to a next faster cache when a valid short pointer to the predicted next memory address is present in the cache line of the hit.

Method of cache prefetching that increases the hit rate of a next faster cache

A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Syndrome data compression for quantum computing devices

Shared mid-level data cache

Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.

Managing memory access requests with prefetch for streams

A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.

Determining thermal time constants of processing systems

In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

Method and apparatus for memory management

A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

Power management across heterogeneous processing units

Growing community of inventors

Portland, OR, United States of America

Srilatha Manne