Intel Corporation

Srikrishnan Venkataraman

Jonathan P Douglas

Michael J Hill

Linda L Hurd

Eric C Samson

William J Lambert

David Gregory Figueroa

Kaladhar Radhakrishnan

Krishna Bharath

Dong Zhong

Alexander Slepoy

Phani Kumar Kandula

Ahmed Abou-Alfotouh

Jayashree Kar

Hector A Aguirre Diaz

Ankush Varma

Charan K Gurumurthy

Sayan Lahiri

Arun Chandrasekhar

Assaf Benhamou

Vijayakumar Ashok Dibbad

Todd W Mellinger

Robert Fite

Narayanan Natarajan

Shamala Chickamenahalli

Priyavadan R Patel

Michael M DeSmith

Muhammed Elgousi

Mallari C Hanchate

Mallari Hanchate

Sudarshan D Solanki

Priyavadan Ramdas Patel

Paul K Tucker

Ahmed Fouad Salama

Chih-Chung Jonathan Wei

Sreedhar Narayanaswamy

A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

System for power throttling

A switchable graphics management scheme, which uses performance/watt information of both the iGPU/dGPU along with system real-time resources like SoC (system-on-chip) thermal, system power budgets to decide on the right GPU for rendering tasks. The scheme uses this threshold power point information along with system resources to determine the optimized GPU for tasks rendering for all applications and use cases. As such, the scheme of adapts to each system design based on capabilities of that specific system.

Apparatus and method to improve switchable graphics system performance and energy consumption based applications and real-time system power/thermal budgets

Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Apparatus and method to reduce power losses in an integrated voltage regulator

Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

Voltage regulator circuitry including module for switching frequency self-optimization

An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second signal via a second delay circuit; and one or more circuitries to tune a first delay of the first delay circuit and a second delay of the second delay circuit, based at least in part on monitoring of a voltage level.

Tunable delay control of a power delivery network

Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time 'T' of the lanes is determined. The number of lanes 'N' in the I/O interface is identified. The programmed lane to lane delay &#x201c;D&#x201d; is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.

Method to control delay between lanes

A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.

Noise reduction method by implementing certain port-to-port delay

In one embodiment, the present invention includes an apparatus having a substrate with vias extending between first and second surfaces thereof, and at least one helical inductor adapted within a via, which may be formed of a conductive material. Other embodiments are described and claimed.

Forming a helical inductor

Growing community of inventors

Bengaluru, India

Srikrishnan Venkataraman