Dell Products Inc.

Srikrishna Ramaswamy

Shyamkumar Thiyagarajan Iyer

Shyam T Iyer

Anirban Kundu

Duk Moon Kim

Gaurav Chawla

Kevin Thomas Marks

Austin Patrick Bolen

Andrew Butcher

Abhijit Shashikant Mirajkar

Glen Sescila

Ragendra K Mishra

Vemuri Sai Krishna

Krishna Kumar P K

Glen Owen Sescila, Iii

A method for managing a data movement operation includes: sending an API configuration to a producer of a first IHS to start implementing a request received from a user; enqueuing a descriptor into a descriptor ring; sending a doorbell signal to notify an SDXI function; fetching the descriptor; analyzing the descriptor to infer a source AKey table entry and a destination AKey table entry; analyzing the source AKey table entry to infer an RKey index and a source IP address index; analyzing the destination AKey table entry to infer a destination IP address index; verifying the SDXI function is allowed to access a source buffer of the first IHS; obtaining the data from the source buffer based on the source IP address index; and moving the data to a destination buffer of the second IHS using a TCP connection.

Method and system for extending SDXI to include IP addresses

A system or method for offloading data operations to a field programmable gate array (FPGA), that includes loading, by the FPGA, a descriptor ring, performing a first lookup, in the descriptor ring, to identify a first descriptor entry, identifying, in the first descriptor entry, a first data operation, making a first determination that the first data operation is unavailable in any of a plurality of module slots of the FPGA, and based on the first determination, loading a first operation module, matching the first data operation, into a first swappable module slot of the plurality of module slots.

Systems and methods for transparent FPGA reconfiguration

An information handling system includes a publisher device and an offload device. Multiple subscriber devices are associated with the publisher device. The offload device communicates with the publisher device. The offload device receives a packet transmission from the publisher device, and translates a topic address of the packet transmission to multiple destination addresses. The offload device sends the packet transmission to each of the subscriber devices. Each of the subscriber devices is associated with a corresponding destination address of the multiple destination address. The offload device receives one or more acknowledgements from the subscriber devices, and combines the one or more acknowledgements into a composite completion message. The offload device sends the composite completion message to the publisher device.

System and method to offload point to multipoint transmissions

Systems and methods for I/O acceleration in a virtualized system include receiving, at a hypervisor from an application executing under a guest OS, a request to write new data to a RAID system, redirecting the request to the VSA owning the RAID drives, moving the new data from guest OS physical address space to VSA physical address space, preparing, by a RAID driver in the VSA, the new data for writing according to a RAID redundancy policy, reading, by the RAID driver into a first buffer, old data and old parity information, performing, by an architectural data mover, inline XOR copy operations to compute a difference between the old and new data, compute new parity information, and write the difference and new parity information into the second buffer, and writing, by the RAID driver, the difference and new parity information to the RAID system using the redundancy policy.

Architectural data mover for RAID XOR acceleration in a virtualized storage appliance

An information handling system reduces latency of input/output transactions. The information handling system includes a system memory and an accelerator. The accelerator intercepts a command response that is issued by the system memory, determines a correct drive from an incorrect drive based on an attribute of the command response, and maps an address of the command response and sends the command response to the correct drive. The no-response command is sent to the incorrect drive. The correct drive completes the command response, and the incorrect drive issues a response that is disregarded by the accelerator.

Apparatus and method for reducing latency of input/output transactions in an information handling system using no-response commands

A queue-based non-volatile memory (NVM) hardware assist card, information handling system, and method are disclosed herein. An embodiment of the queue-based NVM hardware assist card includes a plurality of downstream ports configured to be connected to a corresponding plurality of actual queue-based NVM storage devices, a plurality of upstream ports configured to appear as a plurality of apparent queue-based NVM storage devices, and a distinct upstream port of a different type than the plurality of upstream ports, the distinct upstream port for interacting with a host processor to receive a consolidated processing NVM command from and to return a consolidated processing NVM command completion indication, the queue-based NVM hardware assist card configured to aggregate multiple of the NVM command completion messages received via respective ones of the plurality of downstream ports from respective ones of the plurality of actual queue-based NVM storage devices and to generate the consolidated processing NVM command completion indication.

Method and apparatus for non-volatile memory array improvement using a command aggregation circuit

An information handling system includes an accelerator that advertises, via a single peripheral component interconnect express endpoint, to a processor a plurality of queues from different drives. The processor writes commands and maps each command to target a particular one of the queues. The accelerator performs a queue level logical separation for the mapped command to be processed by the target queue.

System and method for accelerating performance of non-volatile memory RAID stacks

An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.

System and method for improving peripheral component interface express bus performance in an information handling system

An information handling system includes a processor configured to write a first command stride and a second command stride. Each of the first command stride and the second command stride includes logical commands in a single queue, and each of the logical commands is mapped for processing by a peripheral component interconnect express (PCIe). An accelerator may perform a logical separation of the logical commands based on the mapping of each logical command, wherein the logical commands are processed in parallel by the PCIe drives.

System and method of improving efficiency in parallel data processing of a RAID array

In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.

Systems and methods for hardware-based RAID acceleration

In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a plurality of memory storage devices communicatively coupled to the hardware logic device, a plurality of command fetch requests; analyzing metadata associated with each of the plurality of command fetch requests in order to serialize the plurality of command fetch requests in a chronological order; and communicating the coalesced command fetch requests in the chronological order to a memory having stored thereon commands responsive to the coalesced command fetch requests.

Systems and methods for hardware-based raid acceleration for variable-length and out-of-order transactions

In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.

Growing community of inventors

Austin, TX, United States of America

Srikrishna Ramaswamy