Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Srikar Peesari

Daniel Joseph Linnen

Ashish Ghai

Avinash Rajagiri

Dongxiang Liao

Kirubakaran Periyannan

Jagdish Sabde

Shantanu Gupta

Yuvaraj Krishnamoorthy

Deepak Bharadwaj

Rohit Sehgal

Mark Shlick

Shrikar Bhagath

Philip David Reusswig

Ekamdeep Singh

Sukhminder Singh Lobana

Rajan Paudel

Bin Wu

Kalpana Vakati

Maythin Uthayopas

A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.

Encryption detection and backup management

A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.

NAND field use erase plus defect detections

A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Location-based authentication and monitoring for data storage devices

A partial memory die comprises a memory structure that includes a first plane of non-volatile memory cells and a second plane of non-volatile memory cells. The second plane of non-volatile memory cells is incomplete. A first buffer is connected to the first plane. A second buffer is connected to the second plane. A data path circuit is connected to an input interface, the first buffer and the second buffer. The data path circuit is configured to map data received at the input interface and route the mapped data to either the first buffer or the second buffer. An inter-plane re-mapping circuit is connected to the first buffer and the second buffer, and is configured to re-map data from the first buffer and store the re-mapped data in the second buffer for programming into the second plane.

Partial memory die with inter-plane re-mapping

Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Multi-plane memory management

A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Partial memory die

Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.

High-speed data path testing techniques for non-volatile memory

To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.

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San Jose, CA, United States of America

Srikar Peesari