Advanced Micro Devices Corporation

Srikanth Sundararajan

Siu May Ho

Shivananda S Shetty

Mario M Pelella

John JianShi Wang

Paul J Steffan

Jeffrey P Erhardt

W Eugene Hill

Hung-Jen Lin

Franklyn Shihyu Wu

David C Newbury

Chern-Jann Lee

A tester information tester information processing system provides test equipment for generating test data. A markup language encoder connected to the test equipment encodes the test data for storage in an object-oriented database management system connected to the markup language encoder, and a user interface is operatively connected to the object-oriented database management system for retrieval of the test data.

Method and system for storing and retrieving semiconductor tester information

A method and system for fault isolation in semiconductor with devices thereon includes determining test data from a plurality of semiconductor devices and creating a failure bitmap of locations of the plurality of semiconductor devices and test data in a vector graphic CAD format. The vector graphic CAD format allows storage of test data on multiple layers.

Efficient storage of fail data to aid in fault isolation

A system for processing tester information including receiving data from a tester and forming a user defined field for storing descriptive information. A bitmap is created and compressed into a compressed image. The user defined field and the compressed image are then combined into a data structure.

Storage of descriptive information in user defined fields of failure bitmaps in integrated circuit technology development

A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.

Wafer level global bitmap characterization in integrated circuit technology development

Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.

Apparatus and methods for characterizing floating body effects in SOI devices

A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.

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Sunnyvale, CA, United States of America

Srikanth Sundararajan