Bloom Energy Corporation

Sandisk Technologies Inc.

Sandisk Corporation

Nanosys, Inc.

Bloom Energy Coporation

Srikanth Ranganathan

Raghuveer S Makala

J Wallace Parce

Rahul Sharangpani

Chao Liu

Jian Chen

Xiangfeng Duan

Martin Perry

Madhuri Nallabolu

Johann Alsmeier

Arne Watson Ballantine

Fei Zhou

Adarsh Rajashekhar

David Weingaertner

Chockkalingam Karuppaiah

Akio Nishida

Michael Gasda

Sateesh Koka

Andy Ta

Kyle Kekelis

Toshihiro Iizuka

Victor Silva

Vijay Radhakrishnan

Vaibhav Nirgude

Mark Juanitas

Christopher John Petti

Tanmay Kumar

Joel Gamoras

Michael Petrucha

John Fisher

Juan Pablo Saenz

Ming-Che Wu

Nilanjana Basu

Karen Chu Cruden

Paul Bernatis

Ryan Johnson

Sebastian J M Wicklein

Jayakumar Krishnadass

Aniket Pratap

Laxmikant Girwalkar

Madhuri L Nallabolu

A method for operating a fuel cell system is provided. The method includes controlling a provision of fuel to the fuel cell system operating in a steady-state mode. The catalyst sensor is operated by providing a portion of the fuel and anode exhaust generated by the system to the catalyst sensor. Further, a change in an outlet temperature of the catalyst sensor is detected. Thereafter, it is determined whether a reformation catalyst of the catalyst sensor is poisoned by contaminants in the fuel based on the detected change in the outlet temperature.

Fuel cell system containing catalyst based fuel contamination sensor and method of operating thereof

A fuel cell system anode tail gas oxidizer (ATO) includes an inner ATO wall, an outer ATO wall, and a first catalyst ring disposed in a chamber formed between the inner ATO wall and the outer ATO wall. The first catalyst ring includes an inner wall, an outer wall, and a matrix disposed between the inner wall and the outer wall and loaded with an oxidation catalyst.

Fuel cell system including catalyst ring anode tail gas oxidizer

A fuel cell system and method, the system including a hotbox, a fuel cell stack disposed in the hotbox, an anode tail gas oxidizer (ATO) disposed in the hotbox, and a fuel exhaust processor fluidly connected to the hotbox. The fuel exhaust processor includes a first hydrogen pump configured to extract hydrogen from the anode exhaust received from the fuel cell stack and to output the hydrogen to a first hydrogen stream provided to the fuel cell stack, a second hydrogen pump configured to extract hydrogen from anode exhaust output from the first hydrogen pump and to output the hydrogen to the first hydrogen stream, and a third hydrogen pump configured to extract hydrogen from anode exhaust output from the second hydrogen pump and to output the hydrogen to a second hydrogen stream provided to the ATO.

Fuel cell system including fuel exhaust processor and method of operating the same

A fuel cell system includes a fuel cell stack, a fuel inlet conduit configured to provide a fuel to a fuel inlet of the fuel cell stack, an electrochemical pump separator containing an electrolyte, a cathode, and a carbon monoxide tolerant anode, a fuel exhaust conduit that operatively connects a fuel exhaust outlet of the fuel cell stack to an anode inlet of the electrochemical pump separator, and a product conduit which operatively connects a cathode outlet of the electrochemical pump separator to the fuel inlet conduit.

Solid oxide fuel cell system with hydrogen pumping cell with carbon monoxide tolerant anodes and integrated shift reactor

A fuel cell system includes a fuel cell stack configured to generate electricity, an anode exhaust and a cathode exhaust, an anode tail gas oxidizer (ATO) configured to oxidize the anode exhaust using the cathode exhaust, and a low-temperature oxidizer (LTO) configured to catalyze oxidation of carbon monoxide (CO) in the cathode exhaust output from the ATO.

Solid oxide fuel cell system containing low temperature oxidizer and method of operating same with reduced carbon monoxide output

A membrane electrode assembly (MEA) includes an ionically-conductive proton exchange membrane, an anode contacting a first side of the membrane and a cathode contacting a second side of the membrane and including third catalyst particles and a cathode GDL. The anode includes an anode gas diffusion layer (GDL), a first anode catalyst layer containing first catalyst particles, a hydrophobic polymer bonding agent, and a first ionomer bonding agent that lacks functional chains on a molecular backbone, and a second anode catalyst layer containing second catalyst particles and a second ionomer bonding agent that includes functional chains on a molecular backbone.

Catalyst ink compositions and methods for forming hydrogen pumping proton exchange membrane electrochemical cell

A membrane electrode assembly (MEA) includes an ionically-conductive proton exchange membrane. Further, the MEA includes an anode contacting a first side of the membrane. The anode includes an anode gas diffusion layer (GDL). Further, the anode includes a first anode catalyst layer containing first catalyst particles, a hydrophobic polymer bonding agent, and a first ionomer bonding agent that lacks functional chains on a molecular backbone. The anode also includes a second anode catalyst layer containing second catalyst particles and a second ionomer bonding agent that includes functional chains on a molecular backbone. The MEA also includes a cathode contacting a second side of the membrane and comprising third catalyst particles and a cathode GDL.

Membrane electrode assembly (MEA) for proton exchange membrane electrochemical cell

A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.

Randomly writable memory device and method of operating thereof

Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.

Three-dimensional memory device having stressed vertical semiconductor channels and method of making the same

A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000&#xb0; C.

Methods and apparatus for three-dimensional nonvolatile memory

A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.

Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.

Methods and devices for forming nanostructure monolayers and devices including such monolayers

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San Jose, CA, United States of America

Srikanth Ranganathan