Globalwafers Co., Ltd.

Memc Electronic Materials, Inc.

Sunedison Semiconductor Limited (uen201334164h)

Srikanth Kommu

Igor Peidous

Gang Wang

Jeffrey Louis Libbert

Andrew Marquis Jones

Shawn George Thomas

Horacio Josue Mendez

Lu Fei

Alex Usenko

Igor Rapoport

Samuel Christopher Pratt

Leslie George Stanton

Michelle Rene Dickinson

John Allen Pitney

Lance G Hellwig

Andrew M Jones

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

High resistivity semiconductor-on-insulator wafer and a method of manufacture

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of SiGe, SiC, SiGeSn, SiGeSnC, GeSn, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

High resistivity SOI wafers and a method of manufacturing thereof

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Semiconductor on insulator structure comprising a buried high resistivity layer

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

Methods for assessing semiconductor structures

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel includes a charge trapping layer (CTL).

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface

A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of SiGe, SiC, SiGeSn, SiGeSnC, GeSn, group IIIA- nitrides, semiconductor oxides, and any combination thereof.

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St. Charles, MO, United States of America

Srikanth Kommu