Texas Instruments Corporation

Srikanth Gurrapu

Zhongyan Sheng

Yangxi Wang

Described examples include a structured light projector including a light source. The structured light projector also includes a spatial light modulator arranged to modulate light from the light source. The structured light projector also includes a diffractive optical element arranged to modulate the light from the light source. The structured light projector further includes projection optics arranged to project the light modulated by the spatial light modulator and the diffractive optical element to a target.

Structured light projector

An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The interpolation sub-filter that produces the highest sampling frequency is operated first, followed by interpolation sub-filters that operate at successively lower sampling frequencies. Computational independence of the cascaded sub-filters is guaranteed by adding delays to sampled and filtered signals. Delays are implemented by operating each of the cascaded sub-filters using prior filtering results that are computed during a previous sampling interval. A small increment to random-access memory is required for storing the successively delayed signals. The digital signal processor performing the filtering process is stalled for one clock cycle at the time a filtered signal sample is outputted so that the outputted signal sample can be produced without a timing conflict.

Method and apparatus for efficient multi-stage FIR filters

An architecture for a biquad (), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed. The biquad () includes coefficient memory () and data memory (), along with control circuitry () that loads values from these memories () into a coefficient register () and a data register (), respectively. A multiplier () multiplies the values in the coefficient register () and data register (), with the resulting product being stored in a product register (). An accumulator () adds successive product results to derive a new output value in each instance of the IIR filter. A shadow register () temporarily stores the output of the accumulator () from a previous instance, permitting this output to be stored in the data memory () at a later time in the sequence. This permits the order of operations in the second and successive biquads to be altered so that each successive biquad instance can start well before the previous result is derived; as a result, the multiplier () is fed with values each cycle, enabling maximum efficiency operation.

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Plano, TX, United States of America

Srikanth Gurrapu