Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Srikanth Bojja

Bhavin Odedara

Deepak Pancholi

Jayaprakash Naradasi

Srinivasa Rao Sabbineni

Naidu Prasad

Nitin Kumar Gupta

Narendhiran Chinnaanangur Ravimohan

Jayanth Mysore Thimmaiah

Krishnamurthy Dhakshinamurthy

Rampraveen Somasundaram

Raghu Voleti

Anil Kumar Thadi Suryaprakash

Ajay Dhingra

A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.

External clock based clock generator

A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.

Low voltage detection and initialization for non-volatile memory systems

A flip-flop operating with standard threshold voltage MOS devices as compared with high threshold voltage MOS devices may have improved speed performance, but greater leakage current. Likewise, a flip-flop operating with high threshold voltage MOS devices may reduce the leakage current and have better power efficiency, but decreased speed and performance. An optimized flip-flop may include a combination of standard threshold voltage MOS devices and high threshold voltage MOS devices. The optimized flip-flop may have less leakage during stand-by mode as compared to a flip-flop with standard threshold voltage MOS devices. In addition, the optimized flip-flop may have better performance and speed as compared to a flip-flop with high threshold voltage MOS devices.

Optimized flip-flop device with standard and high threshold voltage MOS devices

A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Self-calibrating relaxation oscillator based clock cycle

Self-calibrating relaxation oscillator based clock source

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Bengaluru, India

Srikanth Bojja