Apple Inc.

Intel Corporation

Srikanth Balasubramanian

Tessil Thomas

Ramesh B Gunna

Matthias Knoth

Baskaran Ganesan

Venkatram Krishnaswamy

Satish Shrimali

Aditya Kesiraju

Boris S Alvarez-Heredia

Stefan Rusu

Andrew J Beaumont-Smith

Shih-Chieh Wen

David J Ayers

Daniel U Becker

Richard H Larson

Zhiguo Wang

Stephen M Ramey

Anwar Q Rohillah

Sukirti Gupta

Preethi Bhargavi Sama

An apparatus includes a system-on-chip that includes a plurality of agents configured to generate data transactions, a communication network configured to transfer transactions between two or more of the agents, a plurality of network switches, and a bandwidth regulation circuit. The network switching circuits may be coupled to the agents and to the network. One of the network switches may be configured to estimate a bandwidth need for transactions to be sent via the network switch in an upcoming window. The bandwidth regulation circuit may be configured to moderate power consumption of the network by determining a bandwidth budget using a network power budget for the upcoming time window, and determining a global bandwidth forecast using estimated bandwidth needs received from the network switches. The bandwidth regulation circuit may also be configured to allocate, using the global bandwidth forecast, the bandwidth budget among the network switches.

Network fabric power management

Some aspects of this disclosure relate to a peak power manager that includes a first power estimate accumulator circuit configured to receive one or more power estimates associated with one or more subsystems and to generate a first accumulated power estimate. The peak power manage can further include a first-in first-out (FIFO) storage circuit configured to store a plurality of first accumulated power estimates associated with a plurality of clock cycles corresponding to a moving time interval window. The peak power manager can further include a second power estimate accumulator circuit configured to accumulate the plurality of first accumulated power estimates to generate a second accumulated power estimate and a control circuit. The control circuit can be configured to compare the second accumulated power estimate with a threshold power and generate a control signal to control one or more events at the one or more subsystems in response to the second accumulated power estimate satisfying a condition associated with the threshold power.

Peak power management for processing units

An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

Power sense correction for power budget estimator

In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will not be used for the instruction. In another embodiment, the coprocessor may implement a grid of processing elements in rows and columns, where a given coprocessor instruction may specify an operation that causes up to all of the processing elements to operate on vectors of input operands to produce results. Implementations of the coprocessor may implement a portion of the processing elements. The coprocessor control circuitry may be designed to operate with the full grid or partial grid, reissuing instructions in the partial grid case to perform the requested operation. In still another embodiment, the coprocessor may be able to fuse vector mode operations.

Coprocessors with bypass optimization, variable grid architecture, and fused vector operations

Systems, apparatuses, and methods for implementing an optimized adaptive thermal control mechanism for an integrated circuit (IC) are described. A control unit receives a digital input value which is representative of a temperature of an IC. The control unit compares the input value to at least two set points. A result of a first comparison determines whether an accumulator is incremented or decremented by a programmable gain value. A result of a second comparison determines whether the accumulator is primed with a preset ramp-up value. The preset ramp-up value is used since the accumulator can take several sensing cycles to reach the optimal control value while thermal gradients can become critical in only a few cycles. The output of the accumulator is provided to an actuator which adjusts parameter(s) to modulate the IC's temperature. The granularity and range of the accumulator matches the granularity and range of the actuator.

Adaptive thermal control system

In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.

Operation processing controlled according to difference in current consumption

In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Reducing power consumption of uncore circuitry of a processor

In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.

Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores

Growing community of inventors

Santa Clara, CA, United States of America

Srikanth Balasubramanian