Analog Devices,inc.

Analog Devices Global

Srikanth Aruna Nittala

Mahesh K Madhavan

Jeremy Richard Gorbold

Sanjay Rajasekhar

Roberto S Maurino

Eamonn J Byrne

Abhilasha Kawle

Ramesh Kumar Singh

Asif Ahmad

Shubha Govindachar

Jeremy Gorbold

A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.

Linear and DC-accurate frontend DAC and input structure

A method for correcting digital gain error for a digital code includes receiving the digital code, generating a random number, adding a first dither to the digital code, in which a magnitude of the first dither is determined based on the random number, performing an operation on the digital code including the added dither with a factor to generate a scaled digital code, and subtracting a second dither corresponding to the first dither from the scaled digital code.

System and method for digital gain error correction

The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

High speed parallel procesing digita path for SAR ADC

An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (V). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled Vsignal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same Vnoise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

Successive approximation register analog to digital converter with improved immunity to time varying noise

Parallel digital processing for reducing delay in SAR ADC logic

A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

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East Godavari Dt., India

Srikanth Aruna Nittala